參數(shù)資料
型號(hào)： EPM7512AE
廠商： Altera Corporation
英文描述： Programmable Logic Device Family(MAX7000A可編程邏輯系列器件)
中文描述： 可編程邏輯器件系列（MAX7000A可編程邏輯系列器件）
文件頁(yè)數(shù)： 24/70頁(yè)
文件大小： 1614K
代理商： EPM7512AE
24
Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1)
See the
Operating Requirements for Altera Devices Data Sheet
.
(2)
Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.
(3)
V
CC
must rise monotonically.
(4)
In MAX 7000AE devices, all pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before
V
CCINT
and V
CCIO
are powered.
(5)
These values are specified in
Table 10 on page 22
.
(6)
The parameter is measured with 50
%
of the outputs each sourcing the specified current. The I
OH
parameter refers
to high-level TTL or CMOS output current.
(7)
The parameter is measured with 50
%
of the outputs each sinking the specified current. The I
OL
parameter refers to
low-level TTL or CMOS output current.
(8)
For EPM7128A and EPM7256A devices, this pull-up exists while a device is programmed in-system.
(9)
For MAX 7000AE devices, this pull-up exists while devices are programmed in-system and in unprogrammed
devices during power-up.
(10) Capacitance is measured at 25
°
C and is sample-tested only. The
OE1
pin (high-voltage pin during programming)
has a maximum capacitance of 20 pF.
Figure 10
shows the typical output drive characteristics of MAX 7000A
devices.
Figure 10. Output Drive Characteristics of MAX 7000A Devices
Timing Model
MAX 7000A device timing can be analyzed with the Quartus and
MAX+PLUS II software, with a variety of popular industry-standard
EDA simulators and timing analyzers, or with the timing model shown in
Figure 11
. MAX 7000A devices have predictable internal delays that
enable the designer to determine the worst-case timing of any design. The
MAX+PLUS II software provides timing simulation, point-to-point delay
prediction, and detailed timing analysis for device-wide performance
evaluation.
V
O
Output Voltage (V)
1
2
3
4
1
0
2
0
3
0
4
0
I
OL
I
OH
V
CCINT
= 3.3 V
V
CCIO
= 3.3 V
Room Temperature
5
0
6
0
Typical I
Output
Current (mA)
V
O
Output Voltage (V)
1
2
3
4
1
0
2
0
3
0
4
0
V
CCINT
= 3.3 V
V
CCIO
= 2.5 V
Room Temperature
I
OL
I
OH
5
0
6
0
2.5 V
3.3 V
Typical I
Output
Current (mA)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7512AEBC256-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512AEBC256-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512AEBC256-12 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512AEBC256-7 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7512AEBI256-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 512 Macro 212 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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