Notes to tables: (1) These values are specified under the recommende" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EPM7192EGI160-20
寤犲晢锛� Altera
鏂囦欢闋佹暩(sh霉)锛� 49/66闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MAX 7000 CPLD 192 160-PGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 21
绯诲垪锛� MAX® 7000
鍙法绋嬮鍨嬶細 绯荤当(t菕ng)鍏�(n猫i)鍙法绋�
鏈€澶у欢閬叉檪(sh铆)闁� tpd(1)锛� 20.0ns
闆诲闆绘簮 - 鍏�(n猫i)閮細 4.5 V ~ 5.5 V
閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 12
瀹忓柈鍏冩暩(sh霉)锛� 192
闁€鏁�(sh霉)锛� 3750
杓稿叆/杓稿嚭鏁�(sh霉)锛� 124
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 160-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 160-PBGA锛�39.6x39.6锛�
鍖呰锛� 鎵樼洡
鐢�(ch菐n)鍝佺洰閷勯爜闈細 604 (CN2011-ZH PDF)
鍏跺畠鍚嶇ū锛� 544-2341
Altera Corporation
53
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in Table 14. See Figure 13 for more
information on switching waveforms.
(2)
This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter
must be added to this minimum width if the clear or reset signal incorporates the tLAD parameter into the signal
path.
(3)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4)
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5)
The fMAX values represent the highest frequency for pipelined data.
(6)
Operating conditions: VCCIO = 3.3 V 卤 10% for commercial and industrial use.
(7)
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8)
The tLPA parameter must be added to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parameters for macrocells
running in the low-power mode.
Power
Consumption
Supply power (P) versus frequency (fMAX in MHz) for MAX 7000 devices
is calculated with the following equation:
P = PINT + PIO = ICCINT 脳 VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
The ICCINT value, which depends on the switching frequency and the
application logic, is calculated with the following equation:
ICCINT =
A 脳 MCTON + B 脳 (MCDEV 鈥� MCTON) + C 脳 MCUSED 脳 fMAX 脳 togLC
The parameters in this equation are shown below:
MCTON
= Number of macrocells with the Turbo Bit option turned on,
as reported in the MAX+PLUS II Report File (.rpt)
MCDEV
= Number of macrocells in the device
MCUSED = Total number of macrocells in the design, as reported
in the MAX+PLUS II Report File (.rpt)
fMAX
= Highest clock frequency to the device
togLC
= Average ratio of logic cells toggling at each clock
(typically 0.125)
A, B, C
= Constants, shown in Table 39
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-2WL-CY-F1 CONVERTER MOD DC/DC 28V 50W
EPM7512AEQC208-7N IC MAX 7000 CPLD 512 208-PQFP
VI-2WJ-CY-F4 CONVERTER MOD DC/DC 36V 50W
EPM7512AEQC208-7 IC MAX 7000 CPLD 512 208-PQFP
TAJA156M004RNJ CAP TANT 15UF 4V 20% 1206
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
EPM7192EGI160-7 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Electrically-Erasable Complex PLD
EPM7192EQC160-10 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Electrically-Erasable Complex PLD
EPM7192EQC16012 鍒堕€犲晢:ALTERA 鍔熻兘鎻忚堪:* 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:
EPM7192EQC160-12 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 7000 192 Macro 124 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜(ch菙)椤炲瀷:EEPROM 澶ч浕姹�?c谩i)?sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅�(sh铆)闁�:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100
EPM7192EQC160-15 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 CPLD - MAX 7000 192 Macro 124 IOs RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜(ch菙)椤炲瀷:EEPROM 澶ч浕姹�?c谩i)?sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅�(sh铆)闁�:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100