參數(shù)資料
型號(hào)： EPM7128E
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁(yè)數(shù)： 17/62頁(yè)
文件大?。?/td> 1173K
代理商： EPM7128E
Altera Corporation
17
MAX 7000 Programmable Logic Device Family Data Sheet
f
For more information on using the Jam language, see
(Using the Jam Language for ISP & ICR via an Embedded Processor)
.
The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532
specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Programmable
Speed/Power
Control
MAX 7000 devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50
%
or more,
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 7000
device for either high-speed (i.e., with the Turbo Bit
TM
option turned on)
or low-power (i.e., with the Turbo Bit option turned off) operation. As a
result, speed-critical paths in the design can run at high speed, while the
remaining paths can operate at reduced power. Macrocells that run at low
power incur a nominal timing delay adder (
t
LPA
) for the
t
LAD
,
t
LAC
,
t
IC
,
t
EN
, and
t
SEXP
,
t
ACL
, and
t
CPPW
parameters.
Output
Configuration
MAX 7000 device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
MAX 7000 devices—except 44-pin devices—support the MultiVolt I/ O
interface feature, which allows MAX 7000 devices to interface with
systems that have differing supply voltages. The 5.0-V devices in all
packages can be set for 3.3-V or 5.0-V I/ O pin operation. These devices
have one set of
VCC
pins for internal operation and input buffers
(
VCCINT
), and another set for I/ O output drivers (
VCCIO
).
The
VCCINT
pins must always be connected to a 5.0-V power supply.
With a 5.0-V V
CCINT
level, input voltage thresholds are at TTL levels, and
are therefore compatible with both 3.3-V and 5.0-V inputs.
The
VCCIO
pins can be connected to either a 3.3-V or a 5.0-V power
supply, depending on the output requirements. When the
VCCIO
pins are
connected to a 5.0-V supply, the output levels are compatible with 5.0-V
systems. When V
CCIO
is connected to a 3.3-V supply, the output high is
3.3V and is therefore compatible with 3.3-V or 5.0-V systems. Devices
operating with V
CCIO
levels lower than 4.75 V incur a nominally greater
timing delay of
t
OD2
instead of
t
OD1
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7128ELC84-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128ELC8412 制造商:Altera Corporation 功能描述:
EPM7128ELC84-12 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128ELC8415 制造商:Altera Corporation 功能描述:
EPM7128ELC84-15 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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