參數(shù)資料
型號: EPM7128AETI144-6
廠商: ALTERA CORP
元件分類: PLD
英文描述: EE PLD, 6 ns, PQFP144
封裝: TQFP-144
文件頁數(shù): 28/51頁
文件大?。?/td> 1559K
代理商: EPM7128AETI144-6
628
Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
tPEXP
Parallel expander delay
0.5
0.6
0.5
ns
tLAD
Logic array delay
1.9
2.5
ns
tLAC
Logic control array delay
1.8
2.3
2.5
ns
tIOE
Internal output enable delay
0.0
0.2
ns
tOD1
Output buffer and pad delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
0.3
0.4
0.3
ns
tOD2
Output buffer and pad delay
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
0.8
0.9
0.8
ns
tOD3
Output buffer and pad delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
5.3
5.4
5.3
ns
tZX1
Output buffer enable delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
4.0
ns
tZX2
Output buffer enable delay
slow slew rate = off
VCCIO = 2.5 V
C1 = 35 pF
4.5
ns
tZX3
Output buffer enable delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
9.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
4.0
ns
tSU
Register setup time
1.4
0.8
1.0
ns
tH
Register hold time
0.8
1.0
1.7
ns
tFSU
Register setup time of fast input
0.9
0.8
1.2
ns
tFH
Register hold time of fast input
1.6
1.7
1.3
ns
tRD
Register delay
1.2
1.4
1.6
ns
tCOMB
Combinatorial delay
1.3
1.0
1.6
ns
tIC
Array clock delay
1.9
2.3
2.7
ns
tEN
Register enable time
1.8
2.3
2.5
ns
tGLOB
Global control delay
1.0
0.9
1.1
ns
tPRE
Register preset time
2.3
2.6
2.3
ns
tCLR
Register clear time
2.3
2.6
2.3
ns
tPIA
PIA delay
0.7
0.8
1.3
ns
tLPA
Low-power adder
12.0
11.0
ns
Table 18. MAX 7000AE Internal Timing Parameters (Part 2 of 2)
Notes (1), (7)
Symbol
Parameter
Conditions
Speed Grade
Unit
-4
-5
-6
Min
Max
Min
Max
Min
Max
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