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參數(shù)資料
| 型號： | EPM7128ABI100-7 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | EE PLD, 7.5 ns, PBGA100 |
| 文件頁數(shù)： | 8/51頁 |
| 文件大?。?/td> | 1559K |
| 代理商： | EPM7128ABI100-7 |
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Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Programming
with External
Hardware
MAX 7000A devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the MPU, and the appropriate device
adapter. The MPU performs continuity checking to ensure adequate
electrical contact between the adapter and the device. For more
information, see the Altera Programming Hardware Data Sheet.
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test the
programmed device. For added design verification, designers can
perform functional testing to compare the functional device behavior with
the results of simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers provide programming support for Altera devices. For
more information, see Programming Hardware Manufacturers.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
MAX 7000A devices include the JTAG BST circuitry defined by IEEE Std.
1149.1-1990. Table 4 describes the JTAG instructions supported by
MAX 7000A devices. The pin-out tables starting on page 634 of this data
sheet show the location of the JTAG control pins for each device. If the
JTAG interface is not required, the JTAG pins are available as user I/O
pins.
Table 4. MAX 7000A JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
IDCODE
Selects the IDCODE register and places it between the TDI and TDO pins, allowing the
IDCODE to be serially shifted out of TDO.
USERCODE
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE value to be shifted out of TDO. USERCODE instructions are
available for MAX 7000AE devices only.
UESCODE
These instructions select the user electronic signature (UESCODE) and allow the
UESCODE to be shifted out of TDO. UESCODE instructions are available for EPM7128A
and EPM7256A devices only.
ISP Instructions
These instructions are used when programming MAX 7000A devices via the JTAG ports
with the BitBlaster, ByteBlaster, or ByteBlasterMV download cable, or using a Jam File
(.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an embedded
processor or test equipment.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7128AE | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device |
| EPM7128AEFC100-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7128AEFC100-10N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7128AEFC100-5 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7128AEFC100-5N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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