參數(shù)資料
型號(hào)： EPM7128ABI100-12
廠商： ALTERA CORP
元件分類(lèi)： PLD
英文描述： EE PLD, 12 ns, PBGA100
文件頁(yè)數(shù)： 13/51頁(yè)
文件大?。?/td> 1559K
代理商： EPM7128ABI100-12
614
Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
Open-Drain Output Option
MAX 7000A devices provide an optional open-drain (equivalent to
open-collector) output for each I/O pin. This open-drain output enables
the device to provide system-level control signals (e.g., interrupt and
write enable signals) that can be asserted by any of several devices. It can
also provide an additional wired-OR plane.
Open-drain output pins on MAX 7000A devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of
3.5 V. When the open-drain pin is active, it will drive low. When the pin
is inactive, the trace will be pulled up to 5.0 V by the resistor. The open-
drain pin will only drive low or tri-state; it will never drive high. The rise
time is dependent on the value of the pull-up resistor and load
impedance. The IOL current specification should be considered when
selecting a pull-up resistor.
Programmable Ground Pins
Each unused I/O pin on MAX 7000A devices may be used as an
additional ground pin. In EPM7128A and EPM7256A devices, utilizing
unused I/O pins as additional ground pins requires using the associated
macrocell. In MAX 7000AE devices, this programmable ground feature
does not require the use of the associated macrocell; therefore, the buried
macrocell is still available for user logic.
Slew-Rate Control
The output buffer for each MAX 7000A I/O pin has an adjustable output
slew rate that can be configured for low-noise or high-speed performance.
A faster slew rate provides high-speed transitions for high-performance
systems. However, these fast transitions may introduce noise transients
into the system. A slow slew rate reduces system noise, but adds a
nominal delay of 4 to 5 ns. When the configuration cell is turned off, the
slew rate is set for low-noise performance. Each I/O pin has an individual
EEPROM bit that controls the slew rate, allowing designers to specify the
slew rate on a pin-by-pin basis. The slew rate control affects both the
rising and falling edges of the output signal.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7128AE 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device
EPM7128AEFC100-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-5 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-5N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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