參數(shù)資料
型號： EPM7064AE
廠商： Altera Corporation
英文描述： Programmable Logic Device
中文描述： 可編程邏輯器件
文件頁數(shù)： 50/60頁
文件大?。?/td> 943K
代理商： EPM7064AE
50
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in
Table 11 on page 24
. See
Figure 12
for more information on switching waveforms.
(2)
These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(3)
This minimum pulse width for preset and clear applies for both global clear and array controls. The
t
LPA
parameter
must be added to this minimum width if the clear or reset signal incorporates the
t
LAD
parameter into the signal
path.
(4)
This parameter is measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5)
Operating conditions: V
CCIO
= 2.5
±
0.2 V for commercial and industrial use.
(6)
The
t
LPA
parameter must be added to the
t
LAD
,
t
LAC
,
t
IC
,
t
EN
,
t
SEXP
,
t
ACL
, and
t
CPPW
parameters for macrocells
running in low-power mode.
Power
Consumption
Supply power (P) versus frequency (
f
MAX
, in MHz) for MAX 7000A
devices is calculated with the following equation:
P = P
INT
+ P
IO
= I
CCINT
×
V
CC
+ P
IO
The P
IO
value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices)
.
The I
CCINT
value depends on the switching frequency and the application
logic. The I
CCINT
value is calculated with the following equation:
I
CCINT
=
(A
×
MC
TON
) + [B
×
(MC
DEV
– MC
TON
)] + (C
×
MC
USED
×
f
MAX
×
tog
LC
)
t
RD
t
COMB
t
IC
t
EN
t
GLOB
t
PRE
t
CLR
t
PIA
t
LPA
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
1.6
1.6
2.7
2.5
1.1
2.3
2.3
1.3
11.0
2.0
2.0
3.4
3.1
1.4
2.9
2.9
1.6
10.0
2.7
2.7
4.5
4.2
1.8
3.8
3.8
2.1
10.0
3.2
3.2
5.4
5.0
2.2
4.6
4.6
2.6
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
(6)
Table 27. EPM7256A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-12
Min
Max
Min
Max
Min
Max
Min
Max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7064AEFC100-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064AEFC100-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064AEFC100-4 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064AEFC100-4N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064AEFC100-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
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