參數(shù)資料
型號： EPM7032AETI44-5
廠商： ALTERA CORP
元件分類： PLD
英文描述： EE PLD, 5 ns, PQFP44
封裝： TQFP-44
文件頁數(shù)： 12/51頁
文件大小： 1559K
代理商： EPM7032AETI44-5
596
Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
...and More
Features
s
MultiVoltTM I/O interface enabling device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
s
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
packages
s
Supports hot-socketing in MAX 7000AE devices
s
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
s
Peripheral component interconnect (PCI) compatible
s
Bus friendly architecture including programmable slew-rate control
s
Open-drain output option
s
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
s
Programmable power-up states for macrocell registers in
MAX 7000AE devices
s
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
s
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
s
Programmable security bit for protection of proprietary designs
s
6 to 10 pin- or logic-driven output enable signals
s
Two global clock signals with optional inversion
s
Enhanced interconnect resources for improved routability
s
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
s
Programmable output slew-rate control
s
Programmable ground pins
s
Software design support and automatic place-and-route provided by
Altera’s MAX+PLUS II development system for Windows-based
PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations, and the QuartusTM development system
for Windows-based PCs and Sun SPARCstation and HP 9000
Series 700 workstations
s
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
s
Programming support with Altera’s Master Programming Unit
(MPU), BitBlasterTM serial download cable, and ByteBlasterMVTM
parallel port download cable, as well as programming hardware
from third-party manufacturers and any JamTM File (.jam),
Jam Byte-Code File (.jbc), or Serial Vector Format File- (.svf) capable
in-circuit tester
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7032AETI44-7 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 32 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7032AETI44-7N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 32 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7032B 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device
EPM7032BLC44-3 功能描述:IC MAX 7000 CPLD 32 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:MAX® 7000B 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤
EPM7032BLC44-5 制造商:Rochester Electronics LLC 功能描述: 制造商:Altera Corporation 功能描述:
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