參數資料
型號: EPM3064ATI44-10N
廠商: Altera
文件頁數: 6/46頁
文件大?。?/td> 0K
描述: IC MAX 3000A CPLD 64 44-TQFP
產品變化通告: Bond Wire Change 4/Sept/2008
標準包裝: 480
系列: MAX® 3000A
可編程類型: 系統(tǒng)內可編程
最大延遲時間 tpd(1): 10.0ns
電壓電源 - 內部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數目: 4
宏單元數: 64
門數: 1250
輸入/輸出數: 34
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應商設備封裝: 44-TQFP(10x10)
包裝: 托盤
產品目錄頁面: 603 (CN2011-ZH PDF)
其它名稱: 544-1980
EPM3064ATI44-10N-ND
14
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Programming Sequence
During in-system programming, instructions, addresses, and data are
shifted into the MAX 3000A device through the TDI input pin. Data is
shifted out through the TDO output pin and compared against the
expected data.
Programming a pattern into the device requires the following six ISP
stages. A stand-alone verification of a programmed pattern involves only
stages 1, 2, 5, and 6.
1.
Enter ISP. The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode. The enter ISP stage requires
1ms.
2.
Check ID. Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase. Erasing the device in-system involves shifting in the
instructions to erase the device and applying one erase pulse of
100 ms.
4.
Program. Programming the device in-system involves shifting in the
address and data and then applying the programming pulse to
program the EEPROM cells. This process is repeated for each
EEPROM address.
5.
Verify. Verifying an Altera device in-system involves shifting in
addresses, applying the read pulse to verify the EEPROM cells, and
shifting out the data for comparison. This process is repeated for
each EEPROM address.
6.
Exit ISP. An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode. The exit ISP stage requires
1ms.
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
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