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參數(shù)資料
| 型號： | EPM240T100C5N |
| 廠商： | Altera |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MAX II CPLD 240 LE 100-TQFP |
| 產(chǎn)品變化通告： | Bond Wire Change 4/Sept/2008 |
| 標(biāo)準(zhǔn)包裝： | 270 |
| 系列： | MAX® II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 4.7ns |
| 電壓電源 - 內(nèi)部： | 2.5V，3.3V |
| 邏輯元件/邏輯塊數(shù)目： | 240 |
| 宏單元數(shù)： | 192 |
| 輸入/輸出數(shù)： | 80 |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 603 (CN2011-ZH PDF) |
| 其它名稱： | 544-1964 EPM240T100C5N-ND |
1–4
Chapter 1: Introduction
Referenced Documents
MAX II devices have an internal linear voltage regulator which supports external
supply voltages of 3.3 V or 2.5 V, regulating the supply down to the internal operating
voltage of 1.8 V. MAX IIG and MAX IIZ devices only accept 1.8 V as the external
supply voltage. MAX IIZ devices are pin-compatible with MAX IIG devices in the
100-pin Micro FineLine BGA and 256-pin Micro FineLine BGA packages. Except for
external supply voltage requirements, MAX II and MAX II G devices have identical
pin-outs and timing specifications. Table 1–5 shows the external supply voltages
supported by the MAX II family.
Referenced Documents
This chapter references the following documents:
■
DC and Switching Characteristics chapter in the MAX II Device Handbook
■
Document Revision History
Table 1–6 shows the revision history for this chapter.
Table 1–5. MAX II External Supply Voltages
Devices
EPM240
EPM570
EPM1270
EPM2210
EPM240G
EPM570G
EPM1270G
EPM2210G
EPM240Z
EPM570Z (1)
MultiVolt core external supply voltage (V
CCINT) (2)
3.3 V, 2.5 V
1.8 V
MultiVolt I/O interface voltage levels (V
CCIO)
1.5 V, 1.8 V, 2.5 V, 3.3 V
Notes to Table 1–5:
(1) MAX IIG and MAX IIZ devices only accept 1.8 V on their VCCINT pins. The 1.8-V VCCINT external supply powers the device core directly.
(2) MAX II devices operate internally at 1.8 V.
Table 1–6. Document Revision History
Date and Revision
Changes Made
Summary of Changes
August 2009,
version 1.9
■ Updated Table 1–2.
Added information for speed grade –8
October 2008,
version 1.8
■ Updated “Introduction” section.
■ Updated new Document Format.
—
December 2007,
version1.7
■ Updated Table 1–1 through Table 1–5.
■ Added “Referenced Documents” section.
Updated document with MAX IIZ information.
December 2006,
version 1.6
■ Added document revision history.
—
August 2006,
version 1.5
■ Minor update to features list.
—
July 2006,
version 1.4
■ Minor updates to tables.
—
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM240T100C5N-LJ163174100 | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin TQFP |
| EPM240T100C5NRR | 制造商:Altera 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin TQFP |
| EPM240T100C5RR | 制造商:Altera Corporation 功能描述:CPLD MAX II Family 192 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 100-Pin TQFP |
| EPM240T100I | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM240T100I5 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 192 Macro 80 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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