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參數(shù)資料
| 型號： | EPM240 |
| 廠商： | Altera Corporation |
| 英文描述： | JTAG & In-System Programmability |
| 中文描述： | JTAG接口 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 103K |
| 代理商： | EPM240 |
Altera Corporation
June 2004
Core Version a.b.c variable
3–3
MAX II Device Handbook, Volume 1
JTAG & In-System Programmability
The MAX II device instruction register length is 10 bits and the
USERCODE
register length is 32 bits.
Tables 3–2
and
3–3
show the boundary-scan
register length and device
IDCODE
information for MAX II devices.
f
For JTAG AC characteristics, refer to the chapter on
DC & Switching
Characteristics
. For more information on JTAG BST, see the chapter on
IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
.
JTAG Translator
The JTAG translator feature allows you to access the JTAG TAP and state
signals when either the
USER0
or
USER1
instruction is issued to the JTAG
TAP. The
USER0
and
USER1
instructions bring the JTAG boundary scan
chain (
TDI
) through the user logic instead of the MAX II device’s
boundary scan cells. Each
USER
instruction allows for one unique user-
defined JTAG chain into the logic array.
Table 3–2. MAX II Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EPM240
240
EPM570
480
EPM1270
636
EPM2210
816
Table 3–3. 32-Bit MAX II Device IDCODE
Device
Binary IDCODE (32 Bits)
(1)
HEX IDCODE
Version
(4 Bits)
Part Number
Manufacturer
Identity (11 Bits)
LSB
(1 Bit)
(2)
EPM240
0000
0010 0000 1010 0001
000 0110 1110
1
0x020A10DD
EPM570
0000
0010 0000 1010 0010
000 0110 1110
1
0x020A20DD
EPM1270
0000
0010 0000 1010 0011
000 0110 1110
1
0x020A30DD
EPM2210
0000
0010 0000 1010 0100
000 0110 1110
1
0x020A40DD
Notes to
Table 3–2
:
(1)
The most significant bit (MSB) is on the left.
(2)
The IDCODE's least significant bit (LSB) is always
1
.
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| EPM240_10 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family Data |
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| EPM240F100A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM240F100C | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
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