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參數(shù)資料
| 型號： | EPM2210 |
| 廠商： | Altera Corporation |
| 英文描述： | JTAG & In-System Programmability |
| 中文描述： | JTAG接口 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 103K |
| 代理商： | EPM2210 |
Altera Corporation
June 2004
Core Version a.b.c variable
3–7
MAX II Device Handbook, Volume 1
JTAG & In-System Programmability
Programming Sequence
During in-system programming, 1532 instructions, addresses, and data
are shifted into the MAX II device through the
TDI
input pin. Data is
shifted out through the
TDO
output pin and compared against the
expected data. Programming a pattern into the device requires the
following six ISP steps. A stand-alone verification of a programmed
pattern involves only stages 1, 2, 5, and 6. These steps are automatically
executed by third-party programmers, the Quartus
II software, or the
Jam STAPL and Jam Byte-Code Players.
1.
Enter ISP
– The enter ISP stage ensures that the I/O pins transition
smoothly from user mode to ISP mode.
2.
Check ID
– Before any program or verify process, the silicon ID is
checked. The time required to read this silicon ID is relatively small
compared to the overall programming time.
3.
Bulk Erase
– Erasing the device in-system involves shifting in the
instruction to erase the device and applying an erase pulse(s). The
erase pulse is automatically generated internally by waiting in the
run/test/idle state for the specified erase pulse time of 350 ms.
4.
Program
– Programming the device in-system involves shifting in
the address, data, and program instruction and generating the
program pulse to program the flash cells. The program pulse is
automatically generated internally by waiting in the run/test/idle
state for the specified program pulse time of 75 μs. This process is
repeated for each address in the CFM block.
5.
Verify
– Verifying a MAX II device in-system involves shifting in
addresses, applying the verify instruction to generate the read
pulse, and shifting out the data for comparison. This process is
repeated for each CFM address.
6.
Exit ISP
– An exit ISP stage ensures that the I/O pins transition
smoothly from ISP mode to user mode.
For
TCK
frequencies of 10 MHz, the erase and programming takes less
than one second for EPM240 and EPM570 devices. Erase and
programming times are less than two seconds for EPM1270 and less than
three seconds for the EPM2210 devices. The
TCK
frequency can operate at
up to 25 MHz in MAX II devices providing slight improvements in these
ISP times.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EPM240 | JTAG & In-System Programmability |
| EPM570 | JTAG & In-System Programmability |
| EPM3032A | Programmable Logic Device Family |
| EPM3064A | Programmable Logic Device Family |
| EPM3128A | Programmable Logic Device Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM2210100C5N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m, |
| EPM2210F100A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM2210F100C | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM2210F100I | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM2210F256A5 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 1700 Macro 204 IO RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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