參數(shù)資料
型號: EPF8452AQC160-3
廠商: Altera
文件頁數(shù): 15/62頁
文件大?。?/td> 0K
描述: IC FLEX 8000A FPGA 4K 160-PQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 72
系列: FLEX 8000
LAB/CLB數(shù): 42
邏輯元件/單元數(shù): 336
輸入/輸出數(shù): 120
門數(shù): 4000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
其它名稱: 544-2258
22
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
The signals for the peripheral bus can be generated by any of the four
dedicated inputs or signals on the row interconnect channels, as shown in
Figure 13. The number of row channels in a row that can drive the
peripheral bus correlates to the number of columns in the FLEX 8000
device. EPF8282A and EPF8282AV devices use 13 channels; EPF8452A,
EPF8636A, EPF8820A, and EPF81188A devices use 21 channels; and
EPF81500A devices use 27 channels. The first LE in each LAB is the source
of the row channel signal. The six peripheral control signals (12 in
EPF81500A devices) can be accessed by each IOE.
Figure 13. FLEX 8000 Peripheral Bus
Note:
(1)
n = 13 for EPF8282A and EPF8282AV devices.
n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices.
n = 27 for EPF81500A devices.
Dedicated
Inputs
4
1
2
n
Peripheral Control
Signals
CLR0
CLR1/OE0
CLK0
CLK1/OE1
Row Channels
Programmable
Inversion
OE2
OE3
(OE[4..9])
(1)
Numbers in parentheses are for EPF81500A devices.
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