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參數(shù)資料
| 型號： | EPF8452A |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE LOGIC DEVICES FAMILY |
| 中文描述： | 系列可編程邏輯元件 |
| 文件頁數(shù)： | 10/61頁 |
| 文件大?。?/td> | 979K |
| 代理商： | EPF8452A |
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10
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
The MAX+PLUS II Compiler can create cascade chains automatically
during design processing; designers can also insert cascade chain logic
manually during design entry. Cascade chains longer than eight LEs are
automatically implemented by linking LABs together. The last LE of an
LAB cascades to the first LE in the next LAB in the row.
Figure 5
shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of 4
n
variables implemented with
n
LEs. For a device with an A-2 speed grade,
the LUT delay is approximately 1.6 ns; the cascade chain delay is 0.6 ns.
With the cascade chain, 4.2 ns is needed to decode a 16-bit address.
Figure 5. FLEX 8000 Cascade Chain Operation
LE Operating Modes
The FLEX 8000 LE can operate in one of four modes, each of which uses
LE resources differently. See
Figure 6
. In each mode, seven of the ten
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. The three remaining
inputs to the LE provide clock, clear, and preset control for the register.
The MAX+PLUS II software automatically chooses the appropriate mode
for each application. Design performance can also be enhanced by
designing for the operating mode that supports the desired application.
d[3..0]
LE1
LUT
d[7..4]
LE2
LUT
d[(4n-1)..4(n-1)]
LEn
LUT
d[3..0]
LUT
d[7..4]
LUT
d[(4n-1)..4(n-1)]
LUT
LE1
LE2
LEn
AND Cascade Chain
OR Cascade Chain
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPF8452AGC160-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EPF8452AGC160-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF8452AGI160-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EPF8452ALC84-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EPF8452ALC84-3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 42 LABs 68 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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