Notes to tables: (1) Microparameters are timing delays contributed " />
參數(shù)資料
型號: EPF6024AQC240-3N
廠商: Altera
文件頁數(shù): 35/52頁
文件大?。?/td> 0K
描述: IC FLEX 6000 FPGA 24K 240-PQFP
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 96
系列: FLEX 6000
LAB/CLB數(shù): 196
邏輯元件/單元數(shù): 1960
輸入/輸出數(shù): 199
門數(shù): 24000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 240-BFQFP
供應商設備封裝: 240-PQFP(32x32)
40
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Microparameters are timing delays contributed by individual architectural elements and cannot be measured
explicitly.
(2)
Operating conditions:
VCCIO = 5.0 V ±5% for commercial use in 5.0-V FLEX 6000 devices.
VCCIO = 5.0 V ±10% for industrial use in 5.0-V FLEX 6000 devices.
VCCIO = 3.3 V ±10% for commercial or industrial use in 3.3-V FLEX 6000 devices.
(3)
Operating conditions:
VCCIO = 3.3 V ±10% for commercial or industrial use in 5.0-V FLEX 6000 devices.
VCCIO = 2.5 V ±0.2 V for commercial or industrial use in 3.3-V FLEX 6000 devices.
(4)
Operating conditions:
VCCIO = 2.5 V, 3.3 V, or 5.0 V.
(5)
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
(6)
This timing parameter shows the delay of a register-to-register test pattern and is used to determine speed grades.
There are 12 LEs, including source and destination registers. The row and column interconnects between the
registers vary in length.
(7)
This timing parameter is shown for reference and is specified by characterization.
(8)
This timing parameter is specified by characterization.
Tables 24 through 28 show the timing information for EPF6010A and
EPF6016A devices.
Table 23. External Timing Parameters
Symbol
Parameter
Conditions
tINSU
Setup time with global clock at LE register
tINH
Hold time with global clock at LE register
tOUTCO
Clock-to-output delay with global clock with LE register using FastFLEX I/O
pin
Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part 1 of 2)
Parameter
Speed Grade
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
tREG_TO_REG
1.2
1.3
1.7
ns
tCASC_TO_REG
0.9
1.0
1.2
ns
tCARRY_TO_REG
0.9
1.0
1.2
ns
tDATA_TO_REG
1.1
1.2
1.5
ns
tCASC_TO_OUT
1.3
1.4
1.8
ns
tCARRY_TO_OUT
1.6
1.8
2.3
ns
tDATA_TO_OUT
1.7
2.0
2.5
ns
tREG_TO_OUT
0.4
0.5
ns
tSU
0.9
1.0
1.3
ns
tH
1.4
1.7
2.1
ns
相關PDF資料
PDF描述
VE-BNP-CX CONVERTER MOD DC/DC 13.8V 75W
TAP336K020CRW CAP TANT 33UF 20V 10% RADIAL
ADT7486AARMZ-REEL7 IC TEMP SENS DGTL 2CH SST 10MSOP
EPF6024AQC240-3 IC FLEX 6000 FPGA 24K 240-PQFP
VE-BNN-CX CONVERTER MOD DC/DC 18.5V 75W
相關代理商/技術參數(shù)
參數(shù)描述
EPF6024AQI2083 制造商:Altera Corporation 功能描述:
EPF6024AQI208-3 功能描述:IC FLEX 6000 FPGA 24K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:FLEX 6000 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA(34.55x34.55)
EPF6024ATC100-2 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family
EPF6024ATC144-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 117 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024ATC144-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 117 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256