參數(shù)資料
型號(hào)： EPF6024AQC208-2
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 14/57頁(yè)
文件大?。?/td> 508K
代理商： EPF6024AQC208-2
Altera Corporation
21
FLEX 6000 Programmable Logic Device Family Data Sheet
Table 5 summarizes the FastTrack Interconnect resources available in
each FLEX 6000 device.
In addition to general-purpose I/O pins, FLEX 6000 devices have four
dedicated input pins that provide low-skew signal distribution across the
device. These four inputs can be used for global clock and asynchronous
clear control signals. These signals are available as control signals for all
LEs in the device. The dedicated inputs can also be used as general-
purpose data inputs because they can feed the local interconnect of each
LAB in the device. Using dedicated inputs to route data signals provides
a fast path for high fan-out signals.
The local interconnect from LABs located at either end of two rows can
drive a global control signal. For instance, in an EPF6016 device, LABs C1,
D1, C22, and D22 can all drive global control signals. When an LE drives
a global control signal, the dedicated input pin that drives that signal
cannot be used. Any LE in the device can drive a global control signal by
driving the FastTrack Interconnect into the appropriate LAB. To minimize
delay, however, the Altera software places the driving LE in the
appropriate LAB. The LE-driving-global signal feature is optimized for
speed for control signals; regular data signals are better routed on the
FastTrack Interconnect and do not receive any advantage from being
routed on global signals. This LE-driving-global control signal feature is
controlled by the designer and is not used automatically by the Altera
software. See Figure 11.
Table 5. FLEX 6000 FastTrack Interconnect Resources
Device
Rows
Channels per
Row
Columns
Channels per
Column
EPF6010A
4
144
22
20
EPF6016
EPF6016A
6
144
22
20
EPF6024A
7
186
28
30
相關(guān)PDF資料
PDF描述
EPF6024AQC208-3 LOADABLE PLD, PQFP208
EPF6024AQI208-3 LOADABLE PLD, PQFP208
EPF6024AQC240-1 LOADABLE PLD, PQFP240
EPF6024AQC240-2 LOADABLE PLD, PQFP240
EPF6024AQC240-3 LOADABLE PLD, PQFP240
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF6024AQC208-2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC208-3 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC208-3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC240-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC240-1N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 196 LABs 199 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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