參數(shù)資料
型號： EPF6024AFI256-2
廠商： Altera
文件頁數(shù)： 8/52頁
文件大?。?/td> 0K
描述： IC FLEX 6000 FPGA 24K 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： FLEX 6000
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 1960
輸入/輸出數(shù)： 219
門數(shù)： 24000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
16
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Either the counter enable or the up/down control may be used for a given
counter. Moreover, the synchronous load can be used as a count enable by
routing the register output into the data input automatically when
requested by the designer.
The second LE of each LAB has a special function for counter mode; the
carry-in of the LE can be driven by a fast feedback path from the register.
This function gives a faster counter speed for counter carry chains starting
in the second LE of an LAB.
The Altera software implements functions to use the counter mode
automatically where appropriate. The designer does not have to decide
how the carry chain will be used.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the LAB-wide signals LABCTRL1 and LABCTRL2. The LE
register has an asynchronous clear that can implement an asynchronous
preset. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear
or preset. Because the clear and preset functions are active-low, the Altera
software automatically assigns a logic high to an unused clear or preset
signal. The clear and preset logic is implemented in either the
asynchronous clear or asynchronous preset mode, which is chosen during
design entry (see Figure 8).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF6024AQC208-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC208-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC208-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC208-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024AQC208-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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