參數(shù)資料
型號(hào)： EPF6024ABC256-2
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PBGA256
封裝： BGA-256
文件頁(yè)數(shù)： 16/57頁(yè)
文件大小： 508K
代理商： EPF6024ABC256-2
Altera Corporation
23
FLEX 6000 Programmable Logic Device Family Data Sheet
I/O Elements
An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can
be used as input, output, or bidirectional pins. An IOE receives its data
signals from the adjacent local interconnect, which can be driven by a row
or column interconnect (allowing any LE in the device to drive the IOE) or
by an adjacent LE (allowing fast clock-to-output delays). A FastFLEXTM
I/O pin is a row or column output pin that receives its data signals from
the adjacent local interconnect driven by an adjacent LE. The IOE receives
its output enable signal through the same path, allowing individual
output enables for every pin and permitting emulation of open-drain
buffers. The Altera Compiler uses programmable inversion to invert the
data or output enable signals automatically where appropriate. Open-
drain emulation is provided by driving the data input low and toggling
the OE of each IOE. This emulation is possible because there is one OE per
pin.
A chip-wide output enable feature allows the designer to disable all pins
of the device by asserting one pin (DEV_OE). This feature is useful during
board debugging or testing.
Figure 12 shows the IOE block diagram.
Figure 12. IOE Block Diagram
From LAB Local Interconnect
Slew-Rate
Control
From LAB Local Interconnect
To Row or Column Interconnect
Chip-Wide Output Enable
Delay
相關(guān)PDF資料
PDF描述
EPF6024ABC256-3 LOADABLE PLD, PBGA256
EPF6024ABI256-2 LOADABLE PLD, PBGA256
EPF6024ATC144-1 LOADABLE PLD, PQFP144
EPF6024ATC144-2 LOADABLE PLD, PQFP144
EPF6024ATC144-3 LOADABLE PLD, PQFP144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF6024ABC256-2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024ABC256-3 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6024ABC256-3N 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz CMOS Technology 3.3V 256-Pin BGA 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz 0.42um Technology 3.3V 256-Pin BGA
EPF6024ABI256-2 功能描述:IC FLEX 6000 FPGA 24K 256-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:FLEX 6000 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
EPF6024AFC256-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 6000 196 LABs 219 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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