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參數(shù)資料
| 型號(hào)： | EPF6024A |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(FLEX6000可編程邏輯系列器件) |
| 中文描述： | 可編程邏輯器件系列（FLEX6000可編程邏輯系列器件） |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 241K |
| 代理商： | EPF6024A |
Altera Corporation
919
Understanding
FLEX 6000 Timing
May 1999, ver. 2
Application Note 92
A-AN-092-02
Introduction
Altera
devices provide predictable performance that is consistent from
simulation to application. Before configuring a device, you can determine
the worst-case timing delays for any design by using the MAX+PLUS
II
Timing Analyzer. You can also calculate the propagation delays by using
the timing model provided in this application note along with the timing
parameters listed in the
FLEX 6000 Programmable Logic Device Family Data
Sheet
in this data book.
1
For the most precise timing results, you should use the
MAX+PLUS II Timing Analyzer, which accounts for the effects
of secondary factors such as placement and fan-out.
This application note defines FLEX
6000 device internal and external
timing parameters, and illustrates the timing model for the FLEX 6000
device family.
Familiarity with the FLEX 6000 architecture and characteristics is
assumed. Refer to the
FLEX 6000 Programmable Logic Device Family Data
Sheet
for a complete description of the FLEX 6000 architecture and for
specific values for timing parameters listed in this application note.
Internal Timing
Micropara-
meters
The timing delays contributed by individual FLEX 6000 architectural
elements are called internal timing microparameters, which cannot be
measured explicitly. All internal timing microparameters are shown in
italic type. The following sections define the internal timing
microparameters for the FLEX 6000 device family.
I/O Element Timing Microparameters
The following list describes the I/O element (IOE) timing
microparameters for the FLEX 6000 device family:
t
OD1
Output buffer and pad delay with the slow slew rate
logic option turned off and V
CCIO
= V
CCINT
.
t
OD2
Output buffer and pad delay with the slow slew rate
logic option turned off and V
CCIO
= low voltage.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF6024ABC256-1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024ABC256-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024ABC256-2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024ABC256-3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 196 LABs 218 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6024ABC256-3N | 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz CMOS Technology 3.3V 256-Pin BGA 制造商:Altera Corporation 功能描述:FPGA FLEX 6000 Family 24K Gates 1960 Cells 142.86MHz 0.42um Technology 3.3V 256-Pin BGA |
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