參數(shù)資料
型號: EPF6016AQI208-2
廠商: Altera
文件頁數(shù): 49/52頁
文件大?。?/td> 0K
描述: IC FLEX 6000 FPGA 16K 208-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: FLEX 6000
LAB/CLB數(shù): 132
邏輯元件/單元數(shù): 1320
輸入/輸出數(shù): 171
門數(shù): 16000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
6
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 1. OptiFLEX Architecture Block Diagram
FLEX 6000 devices provide four dedicated, global inputs that drive the
control inputs of the flipflops to ensure efficient distribution of high-
speed, low-skew control signals. These inputs use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect. These inputs can also be driven by internal logic, providing
an ideal solution for a clock divider or an internally generated
asynchronous clear signal that clears many registers in the device. The
dedicated global routing structure is built into the device, eliminating the
need to create a clock tree.
Logic Array Block
An LAB consists of ten LEs, their associated carry and cascade chains, the
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure of the FLEX 6000 architecture, and facilitates
efficient routing with optimum device utilization and high performance.
IOEs
Row FastTrack
Interconnect
Column FastTrack
Interconnect
Column FastTrack
Interconnect
Row FastTrack
Interconnect
Logic Elements
Local Interconnect
(Each LAB accesses
two local interconnect
areas.)
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