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參數(shù)資料
| 型號： | EPF6016AQC208-2N |
| 廠商： | Altera |
| 文件頁數(shù)： | 7/52頁 |
| 文件大小： | 0K |
| 描述： | IC FLEX 6000 FPGA 16K 208-PQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 144 |
| 系列： | FLEX 6000 |
| LAB/CLB數(shù)： | 132 |
| 邏輯元件/單元數(shù)： | 1320 |
| 輸入/輸出數(shù)： | 171 |
| 門數(shù)： | 16000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
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Altera Corporation
15
FLEX 6000 Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications, combinatorial
functions, or wide decoding functions that can take advantage of a
cascade chain. In normal mode, four data inputs from the LAB local
interconnect and the carry-in are inputs to a 4-input LUT. The Altera
software automatically selects the carry-in or the DATA3 signal as one of
the inputs to the LUT. The LUT output can be combined with the cascade-
in signal to form a cascade chain through the cascade-out signal.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, accumulators, and
comparators. An LE in arithmetic mode uses two 3-input LUTs. One LUT
computes a 3-input function; the other generates a carry output. As shown
in Figure 7, the first LUT uses the carry-in signal and two data inputs from
the LAB local interconnect to generate a combinatorial or registered
output. For example, when implementing an adder, this output is the sum
of three signals: DATA1, DATA2, and carry-in. The second LUT uses the
same three signals to generate a carry-out signal, thereby creating a carry
chain. The arithmetic mode also supports simultaneous use of the cascade
chain.
The Altera software implements logic functions to use the arithmetic
mode automatically where appropriate; the designer does not have to
decide how the carry chain will be used.
Counter Mode
The counter mode offers counter enable, synchronous up/down control,
synchronous clear, and synchronous load options. The counter enable and
synchronous up/down control signals are generated from the data inputs
of the LAB local interconnect. The synchronous clear and synchronous
load options are LAB-wide signals that affect all registers in the LAB.
Consequently, if any of the LEs in a LAB use counter mode, other LEs in
that LAB must be used as part of the same counter or be used for a
combinatorial function. In addition, the Altera software automatically
places registers that are not in the counter into other LABs.
The counter mode uses two 3-input LUTs: one generates the counter data
and the other generates the fast carry bit. A 2-to-1 multiplexer provides
synchronous loading, and another AND gate provides synchronous
clearing. If the cascade function is used by an LE in counter mode, the
synchronous clear or load will override any signal carried on the cascade
chain. The synchronous clear overrides the synchronous load.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF6016AQC208-3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 132 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6016AQC208-3N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 132 LABs 171 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF6016AQI208-2 | 功能描述:IC FLEX 6000 FPGA 16K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:FLEX 6000 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| EPF6016AQI2083 | 制造商:ALTERA 功能描述:New |
| EPF6016AQI208-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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