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參數(shù)資料
| 型號(hào)： | EPF10K50SQC208-2X |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁(yè)數(shù)： | 33/120頁(yè) |
| 文件大?。?/td> | 1901K |
| 代理商： | EPF10K50SQC208-2X |
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2
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Note to tables:
(1)
The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
...and More
Features
–
Fabricated on an advanced process and operate with a 2.5-V
internal supply voltage
–
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
–
ClockLockTM and ClockBoostTM options for reduced clock
delay/skew and clock multiplication
–
Built-in low-skew clock distribution trees
–
100% functional testing of all devices; test vectors or scan chains
are not required
–
Pull-up on I/O pins before and during configuration
s
Flexible interconnect
–
FastTrack Interconnect continuous routing structure for fast,
predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Tri-state emulation that implements internal tri-state buses
–
Up to six global clock signals and four global clear signals
s
Powerful I/O pins
–
Individual tri-state output enable control for each pin
–
Open-drain option on each I/O pin
–
Programmable output slew-rate control to reduce switching
noise
–
Clamp to VCCIO user-selectable on a pin-by-pin basis
–
Supports hot-socketing
Table 2. FLEX 10KE Device Features
Feature
EPF10K100E
EPF10K130E
EPF10K200E
EPF10K200S
Typical gates (1)
100,000
130,000
200,000
Maximum system gates
257,000
342,000
513,000
Logic elements (LEs)
4,992
6,656
9,984
EABs
12
16
24
Total RAM bits
49,152
65,536
98,304
Maximum user I/O pins
338
413
470
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| EPF8050MGC560-3 | Field Programmable Gate Array (FPGA) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K50SQC208-3 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K50SQC208-3N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 360 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K50SQC2401 | 制造商:ALTERA 功能描述:* |
| EPF10K50SQC240-1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K50SQC240-1N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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