參數(shù)資料
型號： EPF10K40RC208-3
廠商： Altera
文件頁數(shù)： 89/128頁
文件大小： 0K
描述： IC FLEX 10K FPGA 40K 208-RQFP
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告： Package Change 30/Jun/2010
標準包裝： 48
系列： FLEX-10K®
LAB/CLB數(shù)： 288
邏輯元件/單元數(shù)： 2304
RAM 位總計： 16384
輸入/輸出數(shù)： 147
門數(shù)： 93000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP 裸露焊盤
供應商設備封裝： 240-RQFP（32x32）
其它名稱： 544-2235
Altera Corporation
63
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 36. Interconnect Timing Microparameters
Symbol
Parameter
Conditions
tDIN2IOE
Delay from dedicated input pin to IOE control input
tDCLK2LE
Delay from dedicated clock pin to LE or EAB clock
tDIN2DATA
Delay from dedicated input or clock to LE or EAB data
tDCLK2IOE
Delay from dedicated clock pin to IOE clock
tDIN2LE
Delay from dedicated input pin to LE or EAB control input
tSAMELAB
Routing delay for an LE driving another LE in the same LAB
tSAMEROW
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row
tSAMECOLUMN
Routing delay for an LE driving an IOE in the same column
tDIFFROW
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row
tTWOROWS
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
tLEPERIPH
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
tLABCARRY
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
tLABCASC
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
Table 37. External Timing Parameters
Symbol
Parameter
Conditions
tDRR
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
tINSU
Setup time with global clock at IOE register
tINH
Hold time with global clock at IOE register
tOUTCO
Clock-to-output delay with global clock at IOE register
Table 38. External Bidirectional Timing Parameters
Symbol
Parameter
Condition
tINSUBIDIR
Setup time for bidirectional pins with global clock at adjacent LE register
tINHBIDIR
Hold time for bidirectional pins with global clock at adjacent LE register
tOUTCOBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE register
tXZBIDIR
Synchronous IOE output buffer disable delay
tZXBIDIR
Synchronous IOE output buffer enable delay, slow slew rate = off
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K40RC208-4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 288 LABs 147 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K40RC240-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K40RC240-4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K40RC240-4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 288 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
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