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| 型號(hào)： | EPF10K130EFC672-1X |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁(yè)數(shù)： | 99/120頁(yè) |
| 文件大小： | 1901K |
| 代理商： | EPF10K130EFC672-1X |
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8
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Functional
Description
Each FLEX 10KE device contains an enhanced embedded array to
implement memory and specialized logic functions, and a logic array to
implement general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions, such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a 4-input look-up
table (LUT), a programmable flipflop, and dedicated signal paths for carry
and cascade functions. The eight LEs can be used to create medium-sized
blocks of logic—such as 8-bit counters, address decoders, or state
machines—or combined across LABs to create larger logic blocks. Each
LAB represents about 96 usable gates of logic.
Signal interconnections within FLEX 10KE devices (as well as to and from
device pins) are provided by the FastTrack Interconnect routing structure,
which is a series of fast, continuous row and column channels that run the
entire length and width of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
contains a bidirectional I/O buffer and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 0.9 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
times as low as 3.6 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K130EFC672-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 832 LABs 413 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K130EFC672-2X | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 832 LABs 413 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K130EFC672-3 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 832 LABs 413 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K130EFI484-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 832 LABs 369 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K130EFI484-2K | 制造商:Altera Corporation 功能描述:FLEX 10K FPGA 6656Logic Elements/Macrocells |
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