參數(shù)資料
型號： EPF10K130EFC672-1
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場可編程門陣列（FPGA）
文件頁數(shù)： 69/120頁
文件大?。?/td> 1901K
代理商： EPF10K130EFC672-1
52
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Figure 23. Output Drive Characteristics of FLEX 10KE Devices
Timing Model
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
s
LE register clock-to-output delay (tCO)
s
Interconnect delay (tSAMEROW)
s
LE look-up table delay (tLUT)
s
LE register setup time (tSU)
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Timing simulation and delay prediction are available with the
MAX+PLUS II Simulator and Timing Analyzer, or with industry-
standard EDA tools. The Simulator offers both pre-synthesis functional
simulation to evaluate logic design accuracy and post-synthesis timing
simulation with 0.1-ns resolution. The Timing Analyzer provides point-
to-point timing delay information, setup and hold time analysis, and
device-wide performance analysis.
VO Output Voltage (V)
IOL
IOH
V
VCCINT = 2.5
VCCIO = 2.5
Room Temperature
V
VCCINT = 2.5
VCCIO = 3.3
Room Temperature
12
3
10
20
30
50
60
40
70
80
90
VO Output Voltage (V)
12
3
10
20
30
50
60
40
70
80
90
IOL
O
Typical I
Output
Current (mA)
O
Typical I
Output
Current (mA)
相關(guān)PDF資料
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EPF10K130EFC672-1X Field Programmable Gate Array (FPGA)
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EPF10K200EBC600-3 Field Programmable Gate Array (FPGA)
EPF10K200EBI600-2 Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K130EFC672-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 832 LABs 413 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K130EFC672-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 832 LABs 413 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K130EFC672-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 832 LABs 413 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K130EFC672-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 832 LABs 413 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K130EFI484-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 832 LABs 369 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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