參數(shù)資料
型號： EPF10K10ATI144-3
廠商： Altera
文件頁數(shù)： 42/128頁
文件大小： 0K
描述： IC FLEX 10KA FPGA 10K 144-TQFP
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 180
系列： FLEX-10K®
LAB/CLB數(shù)： 72
邏輯元件/單元數(shù)： 576
RAM 位總計： 6144
輸入/輸出數(shù)： 102
門數(shù)： 31000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
其它名稱： 544-1936
EPF10K10ATI144-3-ND
20
Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a four-input LUT. The Compiler automatically selects the
carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT
output can be combined with the cascade-in signal to form a cascade chain
through the cascade-out signal. Either the register or the LUT can be used
to drive both the local interconnect and the FastTrack Interconnect at the
same time.
The LUT and the register in the LE can be used independently; this feature
is known as register packing. To support register packing, the LE has two
outputs; one drives the local interconnect and the other drives the
FastTrack Interconnect. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a three-input function can be computed in the LUT, and
a fourth independent signal can be registered. Alternatively, a four-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect while the LUT drives the local
interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers 2 three-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a three-input function, and the other generates a carry output.
As shown in Figure 9 on page 19, the first LUT uses the carry-in signal and
two data inputs from the LAB local interconnect to generate a
combinatorial or registered output. For example, in an adder, this output
is the sum of three signals: a, b, and carry-in. The second LUT uses the
same three signals to generate a carry-out signal, thereby creating a carry
chain. The arithmetic mode also supports simultaneous use of the cascade
chain.
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相關代理商/技術參數(shù)
參數(shù)描述
EPF10K10ATI144-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 72 LABs 102 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K10LC84-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 72 LABs 59 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K10LC84-3N 制造商:Altera Corporation 功能描述:FPGA FLEX 10K Family 10K Gates 576 Cells 125MHz CMOS Technology 5V 84-Pin PLCC 制造商:Altera Corporation 功能描述:FPGA FLEX 10K Family 10K Gates 576 Cells 125MHz 0.42um Technology 5V 84-Pin PLCC
EPF10K10LC84-4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 72 LABs 59 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K10LC84-4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 72 LABs 59 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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