參數(shù)資料
型號(hào)： EPF10K100E
廠商： Altera Corporation
英文描述： Embedded Programmable Logic Family(FLEX10KE嵌入式可編程邏輯系列)
中文描述： 嵌入式可編程邏輯系列（FLEX10KE嵌入式可編程邏輯系列）
文件頁(yè)數(shù)： 1/31頁(yè)
文件大?。?/td> 299K
代理商： EPF10K100E
Altera Corporation
869
Understanding
FLEX 10K Timing
May 1999, ver. 2
Application Note 91
A-AN-091-02
Introduction
Altera
devices provide predictable performance that is consistent from
simulation to application. Before configuring a device, you can determine
the worst-case timing delays for any design. You can use the timing
models provided in this application note along with the timing
parameters listed in the
FLEX 10K Embedded Programmable Logic Family
Data Sheet
and
FLEX 10KE Embedded Programmable Logic Device Family
Data Sheet
in this data book to estimate design performance.
1
For the most precise timing results, you should use the
MAX+PLUS
II Timing Analyzer, which accounts for the effects
of secondary factors such as placement and fan-out.
This application note defines FLEX
10K (including FLEX 10KA and
FLEX 10KE) device internal and external timing parameters, and
illustrates the timing model for the FLEX 10K device family.
Familiarity with the FLEX 10K architecture and characteristics is
assumed. Refer to the
FLEX 10K Embedded Programmable Logic Family Data
Sheet
and
FLEX 10KE Embedded Programmable Logic Device Family Data
Sheet
for a complete description of the FLEX 10K architecture and for
specific values for timing parameters listed in this application note.
Internal Timing
Micropara-
meters
The timing delays contributed by individual FLEX 10K architectural
elements, called internal timing microparameters, cannot be measured
explicitly. All internal timing microparameters are shown in italic type.
The following sections define the internal timing microparameters for the
FLEX 10K device family.
I/O Element Timing Microparameters
The following list defines the I/O element (IOE) timing microparameters
for the FLEX 10K device family.
t
IOD
Output data delay. The delay incurred by a signal routed
from the FastTrack
Interconnect to an IOE.
t
IOC
IOE control delay. The delay for a signal used to control
the I/O register’s clock, enable, or clear inputs, or for the
output enable control of the IOE’s tri-state buffer.
相關(guān)PDF資料
PDF描述
EPF10K70 Embedded Programmable Logic Family(FLEX10K嵌入式可編程邏輯系列)
EPF10K10A Embedded Programmable Logic Family(FLEX10K嵌入式可編程邏輯系列)
EPF10K250A Embedded Programmable Logic Family(FLEX10K嵌入式可編程邏輯系列)
EPF10K30 Embedded Programmable Logic Family(FLEX10K嵌入式可編程邏輯系列)
EPF10K200E Embedded Programmable Logic Family(FLEX10KE嵌入式可編程邏輯系列)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K100EBC356-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100EBC356-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EBC356-1N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100EBC356-1X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100EBC356-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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