參數(shù)資料
型號(hào): EPF10K100BFI256-1DX
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 48/120頁
文件大小: 1901K
代理商: EPF10K100BFI256-1DX
Altera Corporation
33
FLEX 10KE Embedded Programmable Logic Family Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral
clears, clock enables, and output enables, two signals on the peripheral
control bus will be used.
Tables 8 and 9 list the sources for each peripheral control signal, and show
how the output enable, clock enable, clock, and clear signals share
12 peripheral control signals. The tables also show the rows that can drive
global signals.
Table 8. Peripheral Bus Sources for EPF10K30E, EPF10K50E & EPF10K50S Devices
Peripheral
Control Signal
EPF10K30E
EPF10K50E
EPF10K50S
OE0
Row A
OE1
Row B
OE2
Row C
Row D
OE3
Row D
Row F
OE4
Row E
Row H
OE5
Row F
Row J
CLKENA0/CLK0/GLOBAL0
Row A
CLKENA1/OE6/GLOBAL1
Row B
Row C
CLKENA2/CLR0
Row C
Row E
CLKENA3/OE7/GLOBAL2
Row D
Row G
CLKENA4/CLR1
Row E
Row I
CLKENA5/CLK1/GLOBAL3
Row F
Row J
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