參數(shù)資料
型號: EPCS1SI8N
廠商: Altera
文件頁數(shù): 9/40頁
文件大?。?/td> 0K
描述: IC CONFIG DEVICE 1MBIT 8-SOIC
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 100
系列: EPCS
可編程類型: 系統(tǒng)內(nèi)可編程
存儲容量: 1Mb
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 604 (CN2011-ZH PDF)
其它名稱: 544-1242-5
EPCS Device Memory Access
Page 17
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Resetting the write enable latch bit to 0 indicates that no write or erase cycle is
accepted. Set the write enable latch bit to 1 before every write bytes, write status, erase
bulk, and erase sector operations.
The non-volatile block protect bits determine the area of the memory protected from
being written or erased unintentionally. Table 9 through Table 13 on page 19 list the
protected area in the EPCS devices with reference to the block protect bits. The erase
bulk operation is only available when all the block protect bits are set to 0. When any
of the block protect bits are set to 1, the relevant area is protected from being written
by a write bytes operation or erased by an erase sector operation.
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