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參數(shù)資料
| 型號(hào)： | EPC2TC32 |
| 廠商： | Altera |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 1.6MBIT 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | EPC |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲(chǔ)容量： | 1.6Mb |
| 電源電壓： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 604 (CN2011-ZH PDF) |
| 其它名稱： | 544-1235 |
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Power and Operation
Page 9
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
configuration bit was sent for the CONF_DONE pin to reach a high state. In this case, the
configuration device pulls its OE pin low, which in turn drives the target device’s
nSTATUS
pin low. Configuration automatically restarts if the Auto-restart
configuration on error
option is turned on in the Quartus II software from the
General
tab of the Device & Pin Options dialog box or the MAX+PLUS II software’s
Global Project Device Options
dialog box (Assign menu).
f For more information about FPGA configuration and configuration interface
connections between configuration devices and Altera FPGAs, refer to the
configuration chapter in the appropriate device handbook.
Power and Operation
This section describes power-on reset (POR) delay, error detection, and 3.3-V and
5.0-V operation of Altera configuration devices.
Power-On Reset
During initial power-up, a POR delay occurs to permit voltage levels to stabilize.
When configuring an FPGA with one EPC1, EPC2, or EPC1441 device, the POR delay
occurs inside the configuration device and the POR delay is a maximum of 200 ms.
When configuring a FLEX 8000 device with one EPC1213, EPC1064, or EPC1064V
device, the POR delay occurs inside the FLEX 8000 device and the POR delay is
typically 100 ms, with a maximum of 200 ms.
During POR, the configuration device drives its OE pin low. This low signal delays
configuration because the OEpin is connected to the target FPGA’s nSTATUS pin. When
the configuration device completes POR, it releases its open-drain OE pin, which is
then pulled high by a pull-up resistor.
1 You should power up the FPGA before the configuration device exits POR to avoid
the master configuration device from entering slave mode.
If the FPGA is not powered up before the configuration device exits POR, the
CONF
_DONE/nCS line is high because of the pull-up resistor. When the configuration
device exits POR and releases OE, it sees nCS high, which signals the configuration
device to enter slave mode. Therefore, configuration will not begin because the DATA
output is tri-stated and DCLK is an input pin in slave mode.
Error Detection Circuitry
The EPC1, EPC2, and EPC1441 configuration devices have built-in error detection
circuitry for configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,
Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, or
Stratix II GX devices.
Built-in error detection circuitry uses the nCS pin of the configuration device, which
monitors the CONF_DONE pin on the FPGA. If the nCS pin on the EPC1 or EPC2 master
device is driven high before all configuration data is transferred, the EPC1 or EPC2
master device drives its OE signal low, which in turn drives the FPGA’s nSTATUS pin
low, indicating a configuration error. Additionally, if the configuration device
generates its data and detects that the CONF_DONE pin has not gone high, it recognizes
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