參數(shù)資料
型號(hào)： EPC1
廠商： Altera Corporation
英文描述： 433800612
中文描述： 配置器件ACEX，頂點(diǎn)，柔性
文件頁(yè)數(shù)： 28/28頁(yè)
文件大?。?/td> 380K
代理商： EPC1
Altera, ACEX, APEX, BitBlaster, ByteBlaster, FLEX, Jam, Master Blaster, MAX+PLUS II, Mercury, Quartus,
and specific device designations, are trademarks and/ or service marks of Altera Corporation in the United
States and other countries. Altera acknowledges the trademarks of other organizations for their respective
products or services mentioned in this document. Altera products are protected under numerous U.S. and
foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of
its semiconductor products to current specifications in accordance with Altera
’
s standard warranty, but
reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by
Altera Corporation. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for
products or services.
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Customer Marketing:
(408) 544-7104
Literature Services:
lit_req@altera.com
Configuration Devices for APEX, ACEX, FLEX & Mercury Devices Data Sheet
28
Altera Corporation
Printed on Recycled Paper.
Table 22. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 &
EPC1064V Devices
Symbol
Parameter
Conditions
EPC1064V
EPC1064
EPC1213
EPC1
EPC1441
Unit
Min Max Min Max Min Max
t
OEZX
t
CSZX
t
CSXZ
t
CSS
t
CSH
t
DSU
t
DH
t
CO
t
CK
f
CK
t
CL
t
CH
t
XZ
t
OEW
t
CASC
t
CKXZ
t
CEOUT
OE
high to
DATA
output enabled
75
50
50
ns
nCS
low to
DATA
output enabled
75
50
50
ns
nCS
high to
DATA
output disabled
75
50
50
ns
nCS
low setup time to first
DCLK
rising edge
150
100
50
ns
nCS
low hold time after
DCLK
rising edge
0
0
0
ns
Data setup time before rising edge on
DCLK
75
50
50
ns
Data hold time after rising edge on
DCLK
0
0
0
ns
DCLK
to
DATA
out delay
100
75
75
ns
Clock period
240
160
100
ns
Clock frequency
4
6
8
MHz
DCLK
low time
120
80
50
ns
DCLK
high time
120
80
50
ns
OE
low or
nCS
high to
DATA
output disabled
75
50
50
ns
OE
pulse width to guarantee counter reset
150
100
100
ns
Last
DCLK
+ 1 to
nCASC
low delay
90
60
50
ns
Last
DCLK
+ 1 to
DATA
tri-state delay
75
50
50
ns
nCS
high to
nCASC
high delay
150
100
100
ns
相關(guān)PDF資料
PDF描述
EPC1 Configuration Devices for SRAM-Based LUT Devices
EPC1064 Configuration Devices for SRAM-Based LUT Devices
EPC1064V Configuration Devices for SRAM-Based LUT Devices
EPC1213 Configuration Devices for SRAM-Based LUT Devices
EPC1441 Configuration Devices for SRAM-Based LUT Devices
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