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參數(shù)資料
| 型號： | EPC1064V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Configuration Devices for SRAM-Based LUT Devices |
| 中文描述： | 配置SRAM器件基于LUT的器件 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 380K |
| 代理商： | EPC1064V |
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16
Altera Corporation
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table5
describes the pin functions of all configuration devices during
FLEX 8000 device configuration.
Notes:
(1)
(2)
(3)
This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only.
This package is available for EPC1441, EPC1064, and EPC1064V devices only.
The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices
support data cascading for FLEX 8000 devices.
f
For more information on FLEX 8000 device configuration, see the
following documents:
ITable 5. Configuration Device Pin Functions During FLEX 8000 Device Configuration
Pin Name
Pin Number
Pin
Type
Description
8-Pin
PDIP
(1)
20-Pin
PLCC
32-Pin
TQFP
(2)
DATA
1
2
31
Output
Serial data output. The
DATA
pin is tri-stated before
configuration when the
nCS
pin is high and after the
configuration device finishes sending its configuration
data. This operation is independent of the device
’
s
position in the cascade chain.
DCLK
2
4
2
Input
DCLK
is a clock input when using EPC1, EPC1213,
EPC1064, and EPC1064V configuration devices. Rising
edges on
DCLK
increment the internal address counter
and present the next bit of data to the
DATA
pin. The
counter is incremented only if the
OE
input is held high,
the
nCS
input is held low, and all configuration data has
not been transferred to the target device.
OE
3
8
7
Open-
Drain
I/O
Input
Output enable (active high) and reset (active low). A low
logic level resets the address counter. A high logic level
enables
DATA
and permits the address counter to count.
nCS
(3)
4
9
10
Chip-select input (active low). A low input allows
DCLK
to
increment the address counter and enables
DATA
.
nCASC
6
12
15
Output
Cascade-select output (active low). This output goes low
when the address counter has reached its maximum
value. The
nCASC
output is usually connected to the
nCS
input of the next device in a configuration chain, so the
next
DCLK
clocks data out of the next device.
Power pin.
Ground Ground pin. A 0.2-
μ
F decoupling capacitor must be
placed between the
VCC
and
GND
pins.
VCC
7, 8
5
20
10
27
12
Power
GND
相關PDF資料 |
PDF描述 |
|---|---|
| EPC1213 | Configuration Devices for SRAM-Based LUT Devices |
| EPC1441 | Configuration Devices for SRAM-Based LUT Devices |
| EPC1064 | Configuration Devices for ACEX, APEX, FLEX & Mercury Devices |
| EPC1064V | Configuration Devices for ACEX, APEX, FLEX & Mercury Devices |
| EPC1213 | Configuration Devices for ACEX, APEX, FLEX & Mercury Devices |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPC1064VLC20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPC1064VLC-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
| EPC1064VLI-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
| EPC1064VPC8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPC1064VPC-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
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