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參數(shù)資料
| 型號： | EPA230-(TD)-50 |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 18K |
| 代理商： | EPA230-(TD)-50 |
20 TTL LOAD
DC Electrical Characteristics
Parameter
Test Conditions
Min
Max Unit
VOH High-Level Output Voltage
VCC= min. VIL = max. IOH = max 2.7
V
VOL
Low-Level Output Voltage
VCC= min. V IH = min. I OL= max
0.5
V
VIK
Input Clamp Voltage
VCC= min. II = IIK
-1.2V
V
IIH
High-Level Input Current
VCC= max. VIN = 2.7V
50
A
IIL
Low-Level Input Current
VCC= max. VIN = 0.5V
-2
mA
IOS
Short Circuit Output Current VCC= max.
-40
-100
mA
ICCH High-Level Supply Current
VCC= max. VIN = OPEN
75
mA
ICCL Low-Level Supply Current
VCC= max. VIN = 0
75
mA
NH
Fanout High-Level Output
VCC= max. VOH = 2.7V
NL
Fanout Low-Level Output
VCC= max. VOL = 0.5V
10 TTL LOAD
EIN
Pulse Input Voltage
3.2
Volts
TRI
Pulse Rise Time
2.0
nS
PWI
Pulse Width
10
nS
P
Period
PWO x2
nS
(For EP9981-5)
20
nS
VCC
Supply Voltage
5.0
Volts
Input Pulse Test Conditions @ 25° C
Unit
VCC
Supply Voltage
4.75
5.25
V
VIH
High-Level Input Voltage
2.0
V
VIL
Low-Level Input Voltage
0.8
V
IIK
Input Clamp Current
-18
mA
IOH
High-Level Output Current
-1.0
mA
IOL
Low-Level Output Current
20
mA
P
Period
PWO x2
nS
PWI
Input Pulse Width
10
nS
TA
Operating Free-Air Temperature
0
+70
°C
Recommended
Operating Conditions
Min
Max
Unit
Package
Schematic
8 Pin DIP Delayed Pulse Width Generator TTL Compatible
Active Delay Line Modules
Features
Precise output pulse width
Positive-edge triggered (10 nS) min.
Fast rise and fall time (4 nS max. measured from 0.75V to 2.4V)
PART
NUMBER**
PULSE
WIDTH *
EPA230-(Td)-5
EPA230-(Td)-6
EPA230-(Td)-7
EPA230-(Td)-8
EPA230-(Td)-9
EPA230-(Td)-10
EPA230-(Td)-15
EPA230-(Td)-20
EPA230-(Td)-25
EPA230-(Td)-30
5 ±1
6 ±1
7 ±1
8 ±1
9 ±1
10 ±1
15 ±1
20 ±1
25 ±1
30 ±1
EPA230-(Td)-35
EPA230-(Td)-40
EPA230-(Td)-50
EPA230-(Td)-60
EPA230-(Td)-70
EPA230-(Td)-75
EPA230-(Td)-80
EPA230-(Td)-90
EPA230-(Td)-100
35 ±1.5
40 ±1.5
50 ±1.5
60 ±1.5
70 ±2
75 ±2
80 ±2
90 ±3
100 ±3
PART
NUMBER**
PULSE
WIDTH *
* Measured at 1.5V Levels
** Td is the delay time (in nS) from trigger pulse
to the leading edge of the output pulse.
DSA230
8/25/94
QAF-CSO1c Rev. B 8/25/94
Unless Otherwise Noted Dimensions in Inches
Tolerances:
Fractional = ± 1/32
.XX = ± .030
.XXX = ± .010
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
TEL: (818) 892-0761
FAX: (818) 894-5791
E L E C T R O N I C S
I N C .
.365
MAX
.300
.500 MAX
.280
PCA
EPA230-Td-5
Date Code
.250
.020
TYP
.010
TYP
MAX
.150 MIN
.020
TYP
MAX
WHITE DOT
PIN#1
VCC
INPUT
1
4
5
8
GND
OUT
DELAY LINE
PULSE
GENERATOR
X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPA230-TD-50 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:8 Pin DIP Delayed Pulse Width Generator TTL Compatible Active Delay Line Modules |
| EPA230-TD-6 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:8 Pin DIP Delayed Pulse Width Generator TTL Compatible Active Delay Line Modules |
| EPA230-TD-60 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:8 Pin DIP Delayed Pulse Width Generator TTL Compatible Active Delay Line Modules |
| EPA230-TD-7 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:8 Pin DIP Delayed Pulse Width Generator TTL Compatible Active Delay Line Modules |
| EPA230-TD-70 | 制造商:PCA 制造商全稱:PCA ELECTRONICS INC. 功能描述:8 Pin DIP Delayed Pulse Width Generator TTL Compatible Active Delay Line Modules |
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