參數(shù)資料
型號(hào)： EP9312
廠商： CIRRUS LOGIC INC
元件分類： 消費(fèi)家電
英文描述： Universal Platform System-on-chip Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA352
封裝： PLASTIC, BGA-352
文件頁(yè)數(shù)： 8/62頁(yè)
文件大?。?/td> 884K
代理商： EP9312
8
Copyright 2005 Cirrus Logic (All Rights Reserved)
DS515PP7
EP9312
Universal Platform SOC Processor
LCD-specific features include:
Timing and interface signals for digital LCD and TFT
displays
Full programmability for either non-interlaced or dual-
scan color and grayscale flat panel displays
Dedicated data path to SDRAM controller for
improved system performance
Pixel depths of 4, 8, 16, or 24 bits per pixel or 256
levels of grayscale
Hardware Cursor up to 64 x 64 pixels
256 x 18 Color Lookup Table
Hardware Blinking
8-bit interface to low-end panel
Touch Screen Interface with 12-bit Analog-
to-digital Converter (ADC)
The touch screen interface performs all sampling,
averaging, ADC range checking, and control for a wide
variety of analog resistive touch screens. This controller
only interrupts the processor when a meaningful change
occurs. The touch screen hardware may be disabled and
the switch matrix and ADC controlled directly if desired.
Features include:
Support for 4-, 5-, 7-, or 8-wire analog resistive touch
screens.
Flexibility - unused lines may be used for temperature
sensing or other functions.
Touch screen interrupt function.
64-Key Keypad Interface
The keypad circuitry scans an 8 x 8 array of 64 normally
open, single-pole switches. Any one or two keys
depressed will be de-bounced and decoded. An interrupt
is generated whenever a stable set of depressed keys is
detected. If the keypad is not utilized, the 16 column/row
pins may be used as general purpose I/O. The Keypad
interface:
Provides scanning, debounce, and decoding for a 64-
key switch array.
Scans an 8-row by 8-column matrix.
May decode 2 keys at once.
Generates an interrupt when a new stable key is
determined.
Also generates a 3-key reset interrupt.
Universal Asynchronous
Receiver/Transmitters (UARTs)
Three 16550-compatible UARTs are supplied. Two
provide asynchronous HDLC (High-level Data Link
Control) protocol support for full duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must
assemble
the
frame
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. A third IrDA
compatible UART is also supplied.
in
memory
before
UART1 supports modem bit rates up to 115.2 Kbps,
supports HDLC and includes a 16 byte FIFO for
Table F. LCD Interface Pin Assignments
Pin Mnemonic
Pin Description
SPCLK
Pixel Clock
P[17:0]
Pixel Data Bus [17:0]
HSYNC / LP
Horizontal
Synchronization / Line Pulse
VCSYNC / FP
Vertical or Composite
Synchronization / Frame Pulse
BLANK
Composite Blank
BRIGHT
Pulse Width Modulated Brightness
Table G. Touch Screen Interface with 12-bit Analog-to-Digital
Converter Pin Assignments
Pin Mnemonic
Pin Description
Xp, Xm
Touch screen ADC X Axis
Yp, Ym
Touch screen ADC Y Axis
SXp, SXm
Touch screen ADC X Axis
Voltage Feedback
SYp, SYm
Touch screen ADC Y Axis
Voltage Feedback
Table H. 64-Key Keypad Interface Pin Assignments
Pin Mnemonic
Pin
Description
Alternative Usage
COL[7:0]
Key Matrix Column
Inputs
General Purpose I/O
ROW[7:0]
Key Matrix Row
Inputs
General Purpose I/O
Table G. Touch Screen Interface with 12-bit Analog-to-Digital
Converter Pin Assignments
Pin Mnemonic
Pin Description
相關(guān)PDF資料
PDF描述
EP9312-CB Universal Platform System-on-chip Processor
EP9312-CBZ Universal Platform System-on-chip Processor
EP9312-EB Universal Platform System-on-chip Processor
EP9312-EBZ Universal Platform System-on-chip Processor
EP9312-IB Universal Platform System-on-chip Processor
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