參數(shù)資料
型號(hào): EP9307-IR
廠商: Cirrus Logic, Inc.
英文描述: ARM9 SOC WITH ETHERNET USB DISPLAY AND TOUCHSCREEN
中文描述: ARM9的系統(tǒng)芯片以太網(wǎng)USB顯示器和觸摸屏
文件頁(yè)數(shù): 14/48頁(yè)
文件大?。?/td> 716K
代理商: EP9307-IR
14
Copyright 2004 Cirrus Logic (All Rights Reserved)
DS667PP3
EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.
Figure 1. Timing Diagram Drawing Key
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements.
T
A
= 0 to 70° C
CVDD = VDD_PLL = 1.8V
RVDD = 3.3 V
All grounds = 0 V
Logic 0 = 0 V, Logic 1 = 3.3 V
Output loading = 50 pF
Timing reference levels = 1.5 V
The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between
33 MHz and 100 MHz (92 MHz for industrial conditions).
Clock
High to Low
High/Low to High
Bus Change
Bus Valid
Undefined/Invalid
Valid Bus to High Impedance State
Bus/Signal Omission
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EP9307-IRZ 432498925
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EP9312-CB Universal Platform System-on-chip Processor
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