Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) DS508F2 EP7312 High-Performance, Low-Power S" />
參數(shù)資料
型號(hào)： EP7312M-CBZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 6/54頁(yè)
文件大?。?/td> 0K
描述： IC ARM720T MCU 74MHZ 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： EP7
核心處理器： ARM7
芯體尺寸： 32-位
速度： 74MHz
連通性： 編解碼器，DAI，EBI/EMI，IrDA，鍵盤(pán)，SPI/Microwire1，UART/USART
外圍設(shè)備： LCD，LED，MaverickKey，PWM
輸入/輸出數(shù)： 27
程序存儲(chǔ)器類型： ROMless
RAM 容量： 56K x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 2.7 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 256-BGA
包裝： 托盤(pán)
配用： 598-1209-ND - KIT DEVELOPMENT EP73XX ARM7
其它名稱： 598-1247
14
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
Note:
1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V
2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
2) Pull-up current = 50 A typical at VDD = 3.3 V.
CI/O
Transceiver capacitance
8
-
10.0
pF
IDD
STANDBY
@ 25 C
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
-
77
41
-
A
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
IDD
STANDBY
@ 70 C
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
-
570
111
A
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
IDD
STANDBY
@ 85 C
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
-
1693
163
A
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD ± 0.1 V,
VIL = GND ± 0.1 V
IDDidle
at 74 MHz
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
-
6
10
-
mA
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD ± 0.1 V, VIL
= GND ± 0.1 V
IDD
IDLE
at 90 MHz
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
-
7
11
-
mA
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD ± 0.1 V, VIL
= GND ± 0.1 V
VDD
STANDBY
Standby supply voltage
2.0
-
V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
a.
Refer to the strength column in the pin assignment tables for all package types.
b.
Assumes buffer has no pull-up or pull-down resistors.
c.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
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