參數(shù)資料
型號(hào): EP7312-EB-90
廠商: Cirrus Logic, Inc.
英文描述: HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
中文描述: 高性能,低功耗的片上系統(tǒng)的SDRAM和增強(qiáng)數(shù)字音頻接口
文件頁數(shù): 24/64頁
文件大?。?/td> 1710K
代理商: EP7312-EB-90
24
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS508PP5
EP7312
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
EXPCLK
nCS
A
nMOE
HALF
WORD
WORD
D
nMWE
EXPRDY
WRITE
t
CSd
t
Ad
t
Ah
t
Ah
t
Ah
t
CSh
t
MOEh
t
MOEd
t
EXs
t
EXh
t
Ds
t
Dh
t
Ds
t
Ds
t
Ds
t
Dh
t
Dh
t
Dh
t
WRd
t
HWd
t
WDd
Figure 9. Static Memory Burst Read Cycle Timing Measurement
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