Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) 33 EP7312 High-Performance, Low-Power S" />
參數(shù)資料
型號: EP7312-CV-90
廠商: Cirrus Logic Inc
文件頁數(shù): 27/54頁
文件大?。?/td> 0K
描述: IC ARM720T MCU 90MHZ 208-LQFP
標準包裝: 36
系列: EP7
核心處理器: ARM7
芯體尺寸: 32-位
速度: 90MHz
連通性: 編解碼器,DAI,EBI/EMI,IrDA,鍵盤,SPI/Microwire1,UART/USART
外圍設(shè)備: LCD,LED,MaverickKey,PWM
輸入/輸出數(shù): 27
程序存儲器類型: ROMless
RAM 容量: 56K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 2.7 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 208-LQFP
包裝: 托盤
配用: 598-1209-ND - KIT DEVELOPMENT EP73XX ARM7
其它名稱: 598-1238
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
33
EP7312
High-Performance, Low-Power System on Chip
38
DSR
I
UART 1 data set ready input
39
nTEST[1]
With p/u*
I
Test mode select input
40
nTEST[0]
With p/u*
I
Test mode select input
41
EINT[3]
I
External interrupt
42
nEINT[2]
I
External interrupt input
43
nEINT[1]
I
External interrupt input
44
nEXTFIQ
I
External fast interrupt input
45
PE[2]/CLKSEL
1
Input
I/O
GPIO port E / clock input
mode select
46
PE[1]/BOOTSEL[1]
1
Input
I/O
GPIO port E / boot mode
select
47
PE[0]/BOOTSEL[0]
1
Input
I/O
GPIO port E / Boot mode
select
48
VSSRTC
RTC Gnd
Real time clock ground
49
RTCOUT
O
Real time clock oscillator
output
50
RTCIN
I
Real time clock oscillator
input
51
VDDRTC
RTC power
Real time clock power, 2.5 V
52
N/C
53
PD[7]/SDQM[1]
1
Low
I/O
GPIO port D / SDRAM byte
lane mask
54
PD[6]/SDQM[0]
1
Low
I/O
GPIO port D / SDRAM byte
lane mask
55
PD[5]
1
Low
I/O
GPIO port D
56
PD[4]
1
Low
I/O
GPIO port D
57
VDDIO
Pad Pwr
Digital I/O power, 3.3 V
58
TMS
with p/u*
I
JTAG mode select
59
PD[3]
1
Low
I/O
GPIO port D
60
PD[2]
1
Low
I/O
GPIO port D
61
PD[1]
1
Low
I/O
GPIO port D
62
PD[0]/LEDFLSH
1
Low
I/O
GPIO port D / LED blinker
output
63
SSICLK
1
Input
I/O
DAI/CODEC/SSI2 serial clock
64
VSSIO
Pad Gnd
I/O ground
65
SSITXFR
1
Low
I/O
DAI/CODEC/SSI2 serial clock
66
SSITXDA
1
Low
O
DAI/CODEC/SSI2 serial data
output
67
SSIRXDA
I
DAI/CODEC/SSI2 serial data
input
68
SSIRXFR
Input
I/O
DAI/CODEC/SSI2 frame sync
69
ADCIN
I
SSI1 ADC serial input
70
nADCCS
1
High
O
SSI1 ADC chip select
71
VSSCORE
Core ground
72
VDDCORE
Core Pwr
Core power, 2.5 V
73
VSSIO
Pad Gnd
I/O ground
74
VDDIO
Pad Pwr
Digital I/O power, 3.3 V
75
DRIVE[1]
2
High /
Low
I/O
PWM drive output
76
DRIVE[0]
2
High /
Low
I/O
PWM drive output
77
ADCCLK
1
Low
O
SSI1 ADC serial clock
78
ADCOUT
1
Low
O
SSI1 ADC serial data output
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Signal
Strength
Reset
State
Type
Description
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