參數(shù)資料
型號: EP7312-CR-90
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
中文描述: 32-BIT, FLASH, 90 MHz, RISC MICROCONTROLLER, PBGA204
封裝: 13 X 13 MM, TFBGA-204
文件頁數(shù): 10/64頁
文件大?。?/td> 1710K
代理商: EP7312-CR-90
10
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS508PP5
EP7312
High-Performance, Low-Power System on Chip
DC-to-DC Converter Interface (PWM)
Provides two 96 kHz clock outputs with
programmable duty ratio (from 1-in-16 to 15-in-16)
that can be used to drivea positiveor negative DC to
DC converter
Table 14
shows the DC-to-DC Converter Interface pin
assignments.
Timers
Internal (RTC) timer
Two internal 16-bit programmable hardware count-
down timers
General Purpose Input/Output (GPIO)
Table 15
shows theGPIO pin assignments.
Three 8-bit and one 3-bit GPIO ports
Supports scanning keyboard matrix
Note:
Pins are multiplexed. See
Table 19 on page 11
for
more information.
Hardware Debug Interface
Full JTAG boundary scan and Embedded ICE
support
Table 16
shows the Hardware Debug Interface pin
assignments.
LED Flasher
A dedicated LED flasher module can be used to generate
a low frequency signal on Port D pin 0 for the purposeof
blinking an LED without CPU intervention. The LED
flasher feature is ideal as a visual annunciator in battery
powered applications, such as a voice mail indicator on a
portable phone or an appointment reminder on a PDA.
Table 17
shows theLED Flasher pin assignments.
Softwareadjustableflash period and duty cycle
Operates from 32 kHz RTC clock
Will continue to flash in IDLE and STANDBY states
4 mA drive current
Note:
Pins are multiplexed. See
Table 19 on page 11
for
more information.
Internal Boot ROM
The internal 128-byte Boot ROM facilitates download of
saved code to the on-board SRAM/ FLASH.
Packaging
The EP7312 is available in a 208-pin LQFP package, 256-
ball PBGA package, or a 204-ball TFBGA package.
Table 14. DC-to-DC Converter Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
DRIVE[1:0]
I/O
PWM drive output
FB[1:0]
I
PWM feedback input
Table 15. General Purpose Input/Output Pin Assignments
Pin Mnemonic
I/O
Pin Description
PA[7:0]
I/O
GPIO port A
PB[7:0]
I/O
GPIO port B
PD[0]/LEDFLSH
(Note)
I/O
GPIO port D
PD[5:1]
I/O
GPIO port D
PD[7:6]/SDQM[1:0]
(Note)
I/O
GPIO port D
PE[1:0]/BOOTSEL[1:0] (Note)
I/O
GPIO port E
PE[2]/CLKSEL
(Note)
I/O
GPIO port E
Table 16. Hardware Debug Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
TCLK
I
JTAG clock
TDI
I
JTAG data input
TDO
O
JTAG data output
nTRST
I
JTAG async reset input
TMS
I
JTAG mode select
Table 17. LED Flasher Pin Assignments
Pin Mnemonic
I/O
Pin Description
PD[0]/LEDFLSH
(Note)
O
LED flasher driver
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