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29
4341H–MP3–10/07
AT8xC51SND2C/MP3B
7.4
Registers
Table 7-4.
PSW Register
PSW (S:D0h) – Program Status Word Register
Reset Value = 0000 0000b
Table 7-5.
AUXR Register
AUXR (S:8Eh) – Auxiliary Control Register
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Bit Number
Bit
Mnemonic
Description
7
CY
Carry Flag
Carry out from bit 1 of ALU operands.
6
AC
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
5
F0
User Definable Flag 0
4 - 3
RS1:0
Register Bank Select Bits
2
OV
Overflow Flag
Overflow set by arithmetic operations.
1
F1
User Definable Flag 1
0
P
Parity Bit
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
7
6
5
4
3
2
1
0
-
EXT16
M0
DPHDIS
XRS1
XRS0
EXTRAM
AO
Bit Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
EXT16
External 16-bit Access Enable Bit
Set to enable 16-bit access mode during MOVX instructions.
Clear to disable 16-bit access mode and enable standard 8-bit access mode during
MOVX instructions.
5
M0
External Memory Access Stretch Bit
Set to stretch RD or WR signals duration to 15 CPU clock periods.
Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
4
DPHDIS
DPH Disable Bit
Set to disable DPH output on P2 when executing MOVX @DPTR instruction.
Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.
3 - 2
XRS1:0
Expanded RAM Size Bits
Refer to
Table 7-2 for ERAM size description.