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6
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
64-Keypad Interface
Matrix keyboards and keypads can be easily read by the
EP7311.
A
dedicated
8-bit
generates strobes for each keyboard column signal. The
pins of Port A, when configured as inputs, can be
selectively
OR'ed
together to provide a keyboard
interrupt that is capable of waking the system from a
STANDBY or IDLE state.
column
driver
output
Column outputs can beindividually set high with the
remaining bits left at high-impedance
Column outputs can be driven all-low, all-high, or all-
high-impedance
Keyboard interruptdriven by OR'ing together all Port
A bits
Keyboard interrupt can beused to wake up the
system
8
×
8 keyboard matrix usable with no external logic,
extra keys can beadded with minimal glue logic
Interrupt Controller
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the
same time, a fixed priority system determines the order
in which they are handled. The EP7311 interrupt
controller has two interrupt types: interrupt request
(IRQ) and fast interrupt request (FIQ). The interrupt
controller has the ability to control interrupts from 22
different FIQ and IRQ sources.
Supports 22 interrupts from a variety of sources (such
as UARTs, SSI1, and key matrix.)
Routes interrupt sources to theARM720T’s IRQ or
FIQ (Fast IRQ) inputs
Fivededicated off-chip interruptlinesoperateaslevel
sensitiveinterrupts
.
Note:
Pins are multiplexed. See
Table S on page 8
for more
information.
Real-Time Clock
The EP7311 contains a 32-bit Real Time Clock (RTC) that
can be written to and read from in the same manner as
the timer counters. It also contains a 32-bit output match
register which can be programmed to generate an
interrupt.
Driven by an external 32.768 kHz crystal oscillator
PLL and Clocking
Processor and Peripheral Clocks operatefrom a single
3.6864 MHz crystal or external 13 MHz clock
Programmable clock speeds allow theperipheral bus
to run at 18 MHz when theprocessor is set to 18 MHz
and at 36 MHz when the processor is set to 36, 49 or
74 MHz
Pin Mnemonic
I/O
Pin Description
COL[7:0]
O
Keyboard scanner column drive
Table J. Keypad Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
nEINT[2:1]
I
External interrupt
EINT[3]
I
External interrupt
nEXTFIQ
I
External Fast Interrupt input
nMEDCHG/nBROM
(Note)
I
Media change interrupt input
Table K. Interrupt Controller Pin Assignments
Pin Mnemonic
Pin Description
RTCIN
Real-Time Clock Oscillator Input
RTCOUT
Real-Time Clock Oscillator Output
VDDRTC
Real-Time Clock Oscillator Power
VSSRTC
Real-Time Clock Oscillator Ground
Table L. Real-Time Clock Pin Assignments
Pin Mnemonic
Pin Description
MOSCIN
Main Oscillator Input
MOSCOUT
Main Oscillator Output
VDDOSC
Main Oscillator Power
VSSOSC
Main Oscillator Ground
Table M. PLL and Clocking Pin Assignments