參數(shù)資料
型號(hào): EP7311-IV-90
廠商: Cirrus Logic Inc
文件頁數(shù): 36/42頁
文件大?。?/td> 0K
描述: IC ARM720T MCU 90MHZ 208-LQFP
標(biāo)準(zhǔn)包裝: 36
系列: EP7
核心處理器: ARM7
芯體尺寸: 32-位
速度: 90MHz
連通性: 編解碼器,EBI/EMI,IrDA,鍵盤,多媒體編解碼器,SPI/Microwire1,UART/USART
外圍設(shè)備: LCD,LED,MaverickKey,PWM
輸入/輸出數(shù): 27
程序存儲(chǔ)器類型: ROMless
RAM 容量: 56K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 2.7 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-LQFP
包裝: 托盤
其它名稱: 598-1231
41
4341H–MP3–10/07
AT8xC51SND2C/MP3B
9.3
Registers
Table 9-4.
IEN0 Register
IEN0 (S:A8h) – Interrupt Enable Register 0
Reset Value = 0000 0000b
7
6
5
4
3
2
1
0
EA
EAUD
EMP3
ES
ET1
EX1
ET0
EX0
Bit Number
Bit
Mnemonic
Description
7
EA
Enable All Interrupt Bit
Set to enable all interrupts.
Clear to disable all interrupts.
If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing
its interrupt enable bit.
6
EAUD
Audio Interface Interrupt Enable Bit
Set to enable audio interface interrupt.
Clear to disable audio interface interrupt.
5
EMP3
MP3 Decoder Interrupt Enable Bit
Set to enable MP3 decoder interrupt.
Clear to disable MP3 decoder interrupt.
4
ES
Serial Port Interrupt Enable Bit
Set to enable serial port interrupt.
Clear to disable serial port interrupt.
3
ET1
Timer 1 Overflow Interrupt Enable Bit
Set to enable timer 1 overflow interrupt.
Clear to disable timer 1 overflow interrupt.
2
EX1
External Interrupt 1 Enable bit
Set to enable external interrupt 1.
Clear to disable external interrupt 1.
1
ET0
Timer 0 Overflow Interrupt Enable Bit
Set to enable timer 0 overflow interrupt.
Clear to disable timer 0 overflow interrupt.
0
EX0
External Interrupt 0 Enable Bit
Set to enable external interrupt 0.
Clear to disable external interrupt 0.
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