參數(shù)資料
型號： EP7311-CB-90
廠商： Cirrus Logic Inc
文件頁數(shù)： 35/42頁
文件大?。?/td> 0K
描述： IC ARM720T MCU 90MHZ 256-PBGA
標準包裝： 90
系列： EP7
核心處理器： ARM7
芯體尺寸： 32-位
速度： 90MHz
連通性： 編解碼器，EBI/EMI，IrDA，鍵盤，多媒體編解碼器，SPI/Microwire1，UART/USART
外圍設(shè)備： LCD，LED，MaverickKey，PWM
輸入/輸出數(shù)： 27
程序存儲器類型： ROMless
RAM 容量： 56K x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 2.7 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 256-BGA
包裝： 托盤
其它名稱： 598-1221
40
4341H–MP3–10/07
AT8xC51SND2C/MP3B
9.2
External Interrupts
9.2.1
INT1:0 Inputs
External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to be level-
triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in TCON register
as shown in Figure 9-2. If ITn = 0, INTn is triggered by a low level at the pin. If ITn = 1, INTn is
negative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXn, n = 0 or 1)
in IEN0. Events on INTn set the interrupt request flag IEn in TCON register. If the interrupt is
edge-triggered, the request flag is cleared by hardware when vectoring to the interrupt service
routine. If the interrupt is level-triggered, the interrupt service routine must clear the request flag
and the interrupt must be deasserted before the end of the interrupt service routine.
INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low level sig-
nals as detailed in section “Exiting Power-down Mode”, page 50.
Figure 9-2.
INT1:0 Input Circuitry
9.2.2
KIN0 Inputs
External interrupts KIN0 provides the capability to connect a keyboard. For detailed information
on this inputs, refer to section “Keyboard Interface”, page 204.
9.2.3
Input Sampling
External interrupt pins (INT1:0 and KIN0) are sampled once per peripheral cycle (6 peripheral
clock periods) (see Figure 9-3). A level-triggered interrupt pin held low or high for more than 6
peripheral clock periods (12 oscillator in standard mode or 6 oscillator clock periods in X2 mode)
guarantees detection. Edge-triggered external interrupts must hold the request pin low for at
least 6 peripheral clock periods.
Figure 9-3.
Minimum Pulse Timings
0
1
INT0/1
IT0/1
TCON.0/2
EX0/1
IEN0.0/2
INT0/1
Interrupt
Request
IE0/1
TCON.1/3
Edge-Triggered Interrupt
Level-Triggered Interrupt
1 cycle
>
1 Peripheral Cycle
1 cycle
>
1 Peripheral Cycle
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