參數(shù)資料
型號: EP7309-IR-C
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
中文描述: 32-BIT, FLASH, 74 MHz, RISC MICROCONTROLLER, PBGA204
封裝: 13 X 13 MM, TFBGA-204
文件頁數(shù): 15/46頁
文件大小: 1893K
代理商: EP7309-IR-C
DS507PP1
Copyright 2001 Cirrus Logic (All Rights Reserved)
15
EP7309
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
Figure 4. Static Memory Burst Read Cycle Timing Measurement
EXPCLK
nCS
A
nMOE
HALF
WORD
WORD
D
nMWE
EXPRDY
WRITE
t
CSd
t
Ad
t
Ah
t
Ah
t
Ah
t
CSh
t
MOEh
t
MOEd
t
EXs
t
EXh
t
Ds
t
Dh
t
Ds
t
Ds
t
Ds
t
Dh
t
Dh
t
Dh
t
WRd
t
HWd
t
WDd
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