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參數(shù)資料
| 型號： | EP7309-EV-C |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CONN MOD JACK 8-8 SHIELD TOP TAB |
| 中文描述： | RISC MICROCONTROLLER, PQFP208 |
| 封裝： | LQFP-208 |
| 文件頁數(shù)： | 16/46頁 |
| 文件大?。?/td> | 1893K |
| 代理商： | EP7309-EV-C |
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Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and
77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on
the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where
EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
Figure 5. Static Memory Burst Write Cycle Timing Measurement
EXPCLK
nCS
A
nMOE
HALF
WORD
WORD
D
nMWE
EXPRDY
WRITE
t
CSd
t
Ad
t
MWd
t
MWh
t
MWd
t
MWd
t
MWd
t
MWh
t
MWh
t
MWh
t
Ah
t
Ah
t
Ah
t
EXs
t
EXh
t
CSh
t
Dv
t
Dv
t
Dv
t
Dnv
t
Dnv
t
Dnv
t
Dv
t
HWd
t
WDd
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相關(guān)代理商/技術(shù)參數(shù) |
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| EP7309-IR-C | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE |
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