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| 型號： | EP6101 |
| 廠商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件） |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 227K |
| 代理商： | EP6101 |
972
Altera Corporation
AN 78: Understanding MAX 5000 & Classic Timing
t
SU
Global clock setup time. The time that data must be present at
the input pin before the global (synchronous) clock signal is
asserted at the clock pin.
t
H
Global clock hold time. The time that data must be present at
the input pin after the global clock signal is asserted at the clock
pin.
t
CO1
Global clock to output delay. The time required to obtain a valid
output after the global clock is asserted at the clock pin.
t
CNT
Minimum global clock period. The minimum period
maintained by a globally clocked counter.
t
ASU
Array clock setup time. The time data must be present at an
input pin before an array (asynchronous) clock signal is asserted
at the input pin.
t
AH
Array clock hold time. The time data must be present at an
input pin after an array clock signal is asserted at the input pin.
t
ACO1
Array clock to output delay. The time required to obtain a valid
output after an array clock signal is asserted at an input pin.
t
ACNT
Minimum array clock period. The minimum period maintained
by a counter when it is clocked by a signal from the array.
Timing Models
Timing models are simplified block diagrams that illustrate the
propagation delays through Altera devices. Logic can be implemented on
different paths. You can trace the actual paths used in your design by
examining the equations listed in the MAX+PLUS II Report File (
.rpt
) for
the project. You can then add up the appropriate internal timing
parameters to calculate the propagation delays through the device.
MAX 5000 Devices
The MAX 5000 architecture supports many functions. The macrocell array
provides registered, combinatorial, or flow-through latch operation. The
registers can be clocked from a global clock or through product-term
array clocks, and can be asynchronously preset and cleared. Separate
product terms control the output enable and logic inversion signals. The
array of shared expander product terms provides additional product
terms to implement complex logic.
The MAX 5000 family has single- and multi-LAB devices.
Figure 1
shows
the timing model for the single-LAB EPM5032 device.
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