參數資料
| 型號： | EP4SGX530KH40C3NES |
| 廠商： | Altera |
| 文件頁數： | 51/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX IV GX 530K 1517-HBGA |
| 標準包裝： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB數： | 21248 |
| 邏輯元件/單元數： | 531200 |
| RAM 位總計： | 28033024 |
| 輸入/輸出數： | 744 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1517-BBGA 裸露焊盤 |
| 供應商設備封裝： | 1517-HBGA（42.5x42.5） |
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–47
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Transceiver Datapath PCS Latency
f For more information about:
■
Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the Transceiver
Architecture in Stratix IV Devices chapter.
■
PCIe mode PCS latency, refer to Figure 1-102 in the Transceiver Architecture in
Stratix IV Devices chapter.
■
XAUI mode PCS latency, refer to Figure 1-119 in the Transceiver Architecture in
Stratix IV Devices chapter.
■
GIGE mode PCS latency, refer to Figure 1-128 in the Transceiver Architecture in
Stratix IV Devices chapter.
■
SONET/SDH mode PCS latency, refer to Figure 1-136 in the Transceiver
Architecture in Stratix IV Devices chapter.
■
SDI mode PCS latency, refer to Figure 1-141 in the Transceiver Architecture in Stratix
IV Devices chapter.
■
(OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the Transceiver
Architecture in Stratix IV Devices chapter.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn)
specifications.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
Clock Tree Specifications
Table 1–33 lists the clock tree specifications for Stratix IV devices.
Table 1–33. Clock Tree Performance for Stratix IV Devices
Performance
Unit
Symbol
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Global clock and
Regional clock
800
700
500
MHz
Periphery clock
550
500
MHz
相關PDF資料 |
PDF描述 |
|---|---|
| ASM43DTAN-S189 | CONN EDGECARD 86POS R/A .156 SLD |
| EP4SGX530KH40C3ES | IC STRATIX IV GX 530K 1517-HBGA |
| EP4SGX530HH35C3NES | IC STRATIX IV GX 530K 1152-HBGA |
| EP4SGX530HH35C3ES | IC STRATIX IV GX 530K 1152-HBGA |
| AGM43DTAN-S189 | CONN EDGECARD 86POS R/A .156 SLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EP4SGX530KH40C4 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX530KH40C4ES | 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 1517HBGA 制造商:Altera Corporation 功能描述:IC FPGA 744 I/O 1517HBGA |
| EP4SGX530KH40C4N | 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX530KH40C4NES | 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 1517HBGA 制造商:Altera Corporation 功能描述:IC FPGA 744 I/O 1517HBGA |
| EP4SGX530KH40I3 | 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 744 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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