參數(shù)資料
型號(hào): EP4SGX530KF43I4N
廠商: Altera
文件頁數(shù): 24/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 530K 1760FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Stratix® IV GX
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計(jì): 28033024
輸入/輸出數(shù): 880
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1760-FCBGA
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–22
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Inter-transceiver
block skew in Basic
(PMA Direct) ×N
mode (15)
N < 18 channels
located across
three
transceiver
blocks with the
source CMU
PLL located in
the center
transceiver
block
400
400
400
ps
N
18 channels
located across
four transceiver
blocks with the
source CMU
PLL located in
one of the two
center
transceiver
blocks
650
650
650
ps
CMU0 PLL and CMU1 PLL
Supported Data
Range
600
8500
600
6500
600
6375
Mbps
pll_powerdown
minimum pulse
width
(tpll_powerdown)
—1
s
CMU PLL lock time
from
pll_powerdown
de-assertion
100
100
100
s
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 7 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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