參數(shù)資料
型號： EP4SGX530KF43C2N
廠商： Altera
文件頁數(shù)： 7/82頁
文件大?。?/td> 0K
描述： IC STRATIX IV FPGA 530K 1760FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 21248
邏輯元件/單元數(shù)： 531200
RAM 位總計： 28033024
輸入/輸出數(shù)： 880
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1760-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1760-FCBGA
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–7
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
DC Characteristics
This section lists the supply current, I/O pin leakage current, bus hold, on-chip
termination (OCT) tolerance, input pin capacitance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Handbook.
I/O Pin Leakage Current
Table 1–9 lists the Stratix IV I/O pin leakage current specifications.
VCCR_R
Receiver power (right side)
1.15
1.2
1.25
V
VCCT_L
Transmitter power (left side)
1.15
1.2
1.25
V
VCCT_R
Transmitter power (right side)
1.15
1.2
1.25
V
VCCL_GXBLn (3)
Transceiver clock power (left side)
1.15
1.2
1.25
V
VCCL_GXBRn (3)
Transceiver clock power (right side)
1.15
1.2
1.25
V
VCCH_GXBLn (3)
Transmitter output buffer power (left side)
1.33
1.4
1.47
V
VCCH_GXBRn (3)
Transmitter output buffer power (right side)
1.33
1.4
1.47
V
Notes to Table 1–8:
(1) For the recommended operating conditions for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) Transceiver power supplies do not have power-on-reset circuitry. After initial power-up, violating the transceiver power supply operating
conditions could lead to unpredictable link behavior.
(3) n = 0, 1, 2, or 3.
Table 1–8. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 2 of 2) (1), (2)
Symbol
Description
Minimum
Typical
Maximum
Unit
Table 1–9. I/O Pin Leakage Current for Stratix IV Devices (1)
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0V to VCCIOMAX
-20
—
20
A
IOZ
Tri-stated I/O pin
VO = 0V to VCCIOMAX
-20
—
20
A
Note to Table 1–9:
(1) VREF current refers to the input pin leakage current.
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EP4SGX530KF43C3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX530KF43C3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX530KF43C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX530KF43C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX530KF43I3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 21248 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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