參數(shù)資料
型號(hào)： EP4SGX360KF43I3
廠商： Altera
文件頁(yè)數(shù)： 72/82頁(yè)
文件大小： 0K
描述： IC STRATIX IV FPGA 360K 1760FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 3
系列： Stratix® IV GX
LAB/CLB數(shù)： 14144
邏輯元件/單元數(shù)： 353600
RAM 位總計(jì)： 23105536
輸入/輸出數(shù)： 880
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1760-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1760-FCBGA
1–66
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
S
SW (sampling
window)
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
Single-ended
voltage
referenced I/O
standard
The JEDEC standard for SSTl and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the AC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing, as shown:
Single-Ended Voltage Referenced I/O Standard
T
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-
to-channel-skew)
The timing difference between the fastest and slowest output edges, including tCO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS
measurement (refer to the Timing Diagram figure under SW in this table).
tDUTY
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input
tOUTPJ_IO
Period jitter on the general purpose I/O driven by a PLL
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL
tRISE
Signal low-to-high transition time (20-80%)
U
——
Table 1–54. Glossary Table (Part 3 of 4)
Letter
Subject
Definitions
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
相關(guān)PDF資料
PDF描述
EP4SGX290KF43I3 IC STRATIX IV FPGA 290K 1760FBGA
EP4SGX290KF43C2 IC STRATIX IV FPGA 290K 1760FBGA
EP4SGX530KH40C3 IC STRATIX IV FPGA 530K 1517HBGA
AMC35DRTS-S734 CONN EDGECARD 70POS DIP .100 SLD
EP4SGX290NF45I3N IC STRATIX IV FPGA 290K 1932FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4SGX360KF43I3N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix IV GX 14144 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX360KF43I4 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix IV GX 14144 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX360KF43I4N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix IV GX 14144 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX360NF45C2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix IV GX 14144 LABs 920 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX360NF45C2N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix IV GX 14144 LABs 920 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*